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ST5080A bảng dữ liệu(PDF) 8 Page - STMicroelectronics |
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ST5080A bảng dữ liệu(HTML) 8 Page - STMicroelectronics |
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8 / 32 page  rectly drive an earpiece. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 4 to 7 in register CR6. At- tenuations in the range 0 to -15 dB relative to the maximum level in 1 dB step can be programmed. The input of this programmable amplifier is the summ of several signals which can be selected by writing to register CR4.: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register CR5 VFR+ and VFR- outputsare capable of driving output power level up to 14mW into differentially con- nected load impedance between 100 and 400 Ω. Differential outputs LS+,LS- are intended to di- rectly drive a Loudspeaker. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range 0 to -30 dB rela- tive to the maximum level in 2.0 dB step can be programmed. The input of this programmable am- plifier can be the summ of signals which can be selected by writing to register CR4: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - EAIN input which may be an alternate Ring signal or any voice frequency band limited signal. (An external decoupling capacitor of about 0.1 µF is necessary). Receive voice signal may be directed to output HFO by means of bit HFE in Register CR4. After processing, signal must be re-entered through in- put HFI to Loudspeaker amplifier input. (An exter- nal decoupling capacitor of about 0.1 µF is neces- sary). LS+ and LS- outputs are capable of driving output power level up to 80 mW into 50 Ω differentially connected load impedance at low distortion meet- ing PCM channel specifications. When the signal source is a Ring squarewave signal, power levels up to approximatively 200 mW can be delivered. Anti-acoustic feed-back for loudspeaker to hand- set microphone loop with squelch effect: on chip switchable anti-larsen for loudspeaker to handset microphone feedback is implemented. A 12dB depth gain control on both transmit and receive path is provided to keep constant the loop gain. On the transmit path the 12dB gain control is pro- vided starting from the CR5 transmit gain defini- tion; at the same time, on the receive path the 12dB gain control is provided starting from CR6 receive gain definition. Digital and Control Interface: PIAFE provides a choice of either of two types of Digital Interface for both control data and PCM. For compatibility with systems which use time slot oriented PCM busses with a separate Control In- terface, as used on COMBO I/II families of de- vices, PIAFE functions are described in next sec- tion. Alternatively, for systems in which PCM and con- trol data are multiplexed together using GCI inter- face scheme, PIAFE functions are described in the section following the next one. PIAFE will automatically switch to one of these two types of interface by sensing the MS pin. Due to Line Transceiver clock recovery circuitry, a low jitter may be provided on FS and MCLK clocks. FS and MCLK must be always in phase. For ST5421S Transceiver, as an example, maximun value of jitter amplitude is a step of 65 ns at each GCI frame (125 µs). So, the maximum jitter amplitude is 130 ns pk-pk. COMBO I/II mode. Digital Interface (Fig. 1) FS Frame Sync input determines the beginning of frame. It may have any duration from a single cy- cle of MCLK to a squarewave. Two different rela- tionships may be established between the Frame Sync input and the first time slot of frame by set- ting bit 3 in register CR0. Non delayed data mode is similar to long frame timing on ETC5057/ TS5070 series of devices (COMBO I and COMBO II respectively): first time slot begins nominally coincident with the rising edge of FS. Alternative is to use delayed data mode, which is similar to short frame sync timing on COMBO I or COMBO II, in which FS input must be high at least a half cycle of MCLK earlier the frame beginning. A time slot assignment circuit on chip may be used with both timing modes, allowing connection to one of the two B1 and B2 voice data channels. Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles follow- ing immediately the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles follow- ing immediately time slot B1. In Format 2, time slot B1 is identical to Format 1. Time slot B2 appears two bit slots after time slot B1. This two bits space is left available for inser- tion of the D channel data. Data format is selected by bit FF (2) in register CR0. Time slot B1 or B2 is selected by bit T0 (0) in Control Register CR1. Bit EN (2) in control register CR1 enables or dis- ables the voice data transfer on DX and DR as appropriate. During the assigned time slot, DX ST5080A 8/32 |
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Mô tả tương tự - ST5080A |
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