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ST486DX bảng dữ liệu(PDF) 8 Page - STMicroelectronics |
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ST486DX bảng dữ liệu(HTML) 8 Page - STMicroelectronics |
8 / 34 page HALT Suspend on HALT. HALT = 0: CPU does not enter suspend mode following execution of a HLT instruction HALT = 1: CPU enters suspend mode following execution of a HLT instruction. SUSP Enable Suspend Pins. SUSP = 0: SUSP# input is ignored and SUSPA# output floats. SUSP = 1: SUSP# input and SUSPA# output are enabled. Reg. INDEX = C2h 7 654 3 2 1 0 SUSP BWRT BARB WT1 HALT LOCK-NW WBAK COP/Reserved Table 2 - 2 CCR2 Reg. INDEX = C3h 7 654 3 2 1 0 NMIEN SMI-LOCK Reserved Table 2 - 1 CCR3 ST486DX - SMM IMPLEMENTATION 16 SMI_LOCK SMM Register Lock. SMI_LOCK = 0: Any program in normal mode, as well as SMM software, has access to all Configuration Control Registers. SMI_LOCK = 1: The following Configuration Control Register bits can not be modified unless operating in SMM mode: SMI, SMAC, MMAC, NMIEN, SMI_LOCK, and SMAR register size fields. NMIEN NMI Enable. NMIEN = 0: NMI (Non-Maskable Interrupt) is not recognized during SMM. One occurrence of NMI is latched and serviced after SMM mode is exited. The NMIEN bit should be cleared before executing a RSM instruction to exit SMM. NMIEN = 1: NMI is enabled during SMM. This bit should only be set temporarily while in the SMM routine to allow NMI interrupts to be serviced. NMIEN should not be set |
Số phần tương tự - ST486DX |
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Mô tả tương tự - ST486DX |
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