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LM3S610-IRN50-B0T bảng dữ liệu(PDF) 5 Page - List of Unclassifed Manufacturers

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LM3S610-IRN50-B0T bảng dữ liệu(HTML) 5 Page - List of Unclassifed Manufacturers

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LM3S610 Data Sheet
April 27, 2007
5
Preliminary
10.4
Register Map ..................................................................................................................................... 187
10.5
Register Descriptions......................................................................................................................... 188
11.
Analog-to-Digital Converter (ADC) .................................................................................. 209
11.1
Block Diagram ................................................................................................................................... 209
11.2
Functional Description ....................................................................................................................... 210
11.2.1 Sample Sequencers .......................................................................................................................... 210
11.2.2 Module Control .................................................................................................................................. 211
11.2.3 Hardware Sample Averaging Circuit.................................................................................................. 211
11.2.4 Analog-to-Digital Converter ............................................................................................................... 211
11.2.5 Test Modes ........................................................................................................................................ 211
11.2.6 Internal Temperature Sensor............................................................................................................. 212
11.3
Initialization and Configuration........................................................................................................... 212
11.3.1 Module Initialization ........................................................................................................................... 212
11.3.2 Sample Sequencer Configuration...................................................................................................... 212
11.4
Register Map ..................................................................................................................................... 213
11.5
Register Descriptions......................................................................................................................... 214
12.
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 239
12.1
Block Diagram ................................................................................................................................... 240
12.2
Functional Description ....................................................................................................................... 240
12.2.1 Transmit/Receive Logic ..................................................................................................................... 240
12.2.2 Baud-Rate Generation....................................................................................................................... 241
12.2.3 Data Transmission............................................................................................................................. 242
12.2.4 FIFO Operation .................................................................................................................................. 242
12.2.5 Interrupts............................................................................................................................................ 242
12.2.6 Loopback Operation .......................................................................................................................... 243
12.3
Initialization and Configuration........................................................................................................... 243
12.4
Register Map ..................................................................................................................................... 244
12.5
Register Descriptions......................................................................................................................... 245
13.
Synchronous Serial Interface (SSI) ................................................................................. 275
13.1
Block Diagram ................................................................................................................................... 275
13.2
Functional Description ....................................................................................................................... 276
13.2.1 Bit Rate Generation ........................................................................................................................... 276
13.2.2 FIFO Operation .................................................................................................................................. 276
13.2.3 Interrupts............................................................................................................................................ 276
13.2.4 Frame Formats .................................................................................................................................. 277
13.3
Initialization and Configuration........................................................................................................... 284
13.4
Register Map ..................................................................................................................................... 285
13.5
Register Descriptions......................................................................................................................... 286
14.
Inter-Integrated Circuit (I2C) Interface ............................................................................ 310
14.1
Block Diagram ................................................................................................................................... 310
14.2
Functional Description ....................................................................................................................... 310
14.2.1 I2C Bus Functional Overview............................................................................................................. 311
14.2.2 Available Speed Modes ..................................................................................................................... 320
14.3
Initialization and Configuration........................................................................................................... 321
14.4
Register Map ..................................................................................................................................... 322
14.5
Register Descriptions (I2C Master).................................................................................................... 322
14.6
Register Descriptions (I2C Slave)...................................................................................................... 336


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