Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 338
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 339
Figure 14-13. Slave Command Sequence ............................................................................................ 340
Figure 15-1.
Analog Comparator Module Block Diagram ..................................................................... 364
Figure 15-2.
Structure of Comparator Unit .......................................................................................... 365
Figure 15-3.
Comparator Internal Reference Structure ........................................................................ 366
Figure 16-1.
Pin Connection Diagram ................................................................................................ 375
Figure 19-1.
Load Conditions ............................................................................................................ 386
Figure 19-2.
I2C Timing ..................................................................................................................... 388
Figure 19-3.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 389
Figure 19-4.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 389
Figure 19-5.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 390
Figure 19-6.
JTAG Test Clock Input Timing ......................................................................................... 391
Figure 19-7.
JTAG Test Access Port (TAP) Timing .............................................................................. 391
Figure 19-8.
JTAG TRST Timing ........................................................................................................ 391
Figure 19-9.
External Reset Timing (RST) .......................................................................................... 392
Figure 19-10. Power-On Reset Timing ................................................................................................. 393
Figure 19-11. Brown-Out Reset Timing ................................................................................................ 393
Figure 19-12. Software Reset Timing ................................................................................................... 393
Figure 19-13. Watchdog Reset Timing ................................................................................................. 394
Figure 19-14. LDO Reset Timing ......................................................................................................... 394
Figure 20-1.
48-Pin LQFP Package ................................................................................................... 395
9
October 01, 2007
Preliminary
LM3S608 Microcontroller