6.1.3
Power Control ........................................................................................................................... 52
6.1.4
Clock Control ............................................................................................................................ 52
6.1.5
System Control ......................................................................................................................... 54
6.2
Initialization and Configuration ................................................................................................... 55
6.3
Register Map ............................................................................................................................ 55
6.4
Register Descriptions ................................................................................................................ 56
7
Hibernation Module .......................................................................................................... 102
7.1
Block Diagram ........................................................................................................................ 103
7.2
Functional Description ............................................................................................................. 103
7.2.1
Register Access Timing ........................................................................................................... 103
7.2.2
Clock Source .......................................................................................................................... 104
7.2.3
Battery Management ............................................................................................................... 104
7.2.4
Real-Time Clock ...................................................................................................................... 104
7.2.5
Non-Volatile Memory ............................................................................................................... 105
7.2.6
Power Control ......................................................................................................................... 105
7.2.7
Interrupts and Status ............................................................................................................... 105
7.3
Initialization and Configuration ................................................................................................. 106
7.3.1
Initialization ............................................................................................................................. 106
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 106
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 106
7.3.4
External Wake-Up from Hibernation .......................................................................................... 107
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 107
7.4
Register Map .......................................................................................................................... 107
7.5
Register Descriptions .............................................................................................................. 108
8
Internal Memory ............................................................................................................... 121
8.1
Block Diagram ........................................................................................................................ 121
8.2
Functional Description ............................................................................................................. 121
8.2.1
SRAM Memory ........................................................................................................................ 121
8.2.2
Flash Memory ......................................................................................................................... 122
8.3
Flash Memory Initialization and Configuration ........................................................................... 123
8.3.1
Flash Programming ................................................................................................................. 123
8.3.2
Nonvolatile Register Programming ........................................................................................... 124
8.4
Register Map .......................................................................................................................... 124
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 125
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 132
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 145
9.1
Functional Description ............................................................................................................. 145
9.1.1
Data Control ........................................................................................................................... 145
9.1.2
Interrupt Control ...................................................................................................................... 146
9.1.3
Mode Control .......................................................................................................................... 147
9.1.4
Commit Control ....................................................................................................................... 147
9.1.5
Pad Control ............................................................................................................................. 147
9.1.6
Identification ........................................................................................................................... 147
9.2
Initialization and Configuration ................................................................................................. 147
9.3
Register Map .......................................................................................................................... 148
9.4
Register Descriptions .............................................................................................................. 150
September 02, 2007
4
Preliminary
Table of Contents