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LM3S1110-IQN50-A1T bảng dữ liệu(PDF) 10 Page - List of Unclassifed Manufacturers

tên linh kiện LM3S1110-IQN50-A1T
Giải thích chi tiết về linh kiện  Microcontroller
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nhà sản xuất  ETC2 [List of Unclassifed Manufacturers]
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LM3S1110-IQN50-A1T bảng dữ liệu(HTML) 10 Page - List of Unclassifed Manufacturers

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List of Registers
System Control .............................................................................................................................. 49
Register 1:
Device Identification 0 (DID0), offset 0x000 ....................................................................... 57
Register 2:
Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 59
Register 3:
LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 60
Register 4:
Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 61
Register 5:
Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 62
Register 6:
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 63
Register 7:
Reset Cause (RESC), offset 0x05C .................................................................................. 64
Register 8:
Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 65
Register 9:
XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 69
Register 10:
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 70
Register 11:
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 72
Register 12:
Device Identification 1 (DID1), offset 0x004 ....................................................................... 73
Register 13:
Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 75
Register 14:
Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 76
Register 15:
Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 78
Register 16:
Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 80
Register 17:
Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 82
Register 18:
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 83
Register 19:
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 84
Register 20:
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 85
Register 21:
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 86
Register 22:
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 88
Register 23:
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 90
Register 24:
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 .................................... 92
Register 25:
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................. 94
Register 26:
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ......................... 96
Register 27:
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................... 98
Register 28:
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................... 99
Register 29:
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 101
Hibernation Module ..................................................................................................................... 102
Register 1:
Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 109
Register 2:
Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 110
Register 3:
Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 111
Register 4:
Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 112
Register 5:
Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 113
Register 6:
Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 115
Register 7:
Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 116
Register 8:
Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 117
Register 9:
Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 118
Register 10:
Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 119
Register 11:
Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 120
Internal Memory ........................................................................................................................... 121
Register 1:
Flash Memory Address (FMA), offset 0x000 .................................................................... 126
Register 2:
Flash Memory Data (FMD), offset 0x004 ......................................................................... 127
September 02, 2007
10
Preliminary
Table of Contents


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