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LM3S1110-IRN50-A1T bảng dữ liệu(PDF) 5 Page - List of Unclassifed Manufacturers

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Giải thích chi tiết về linh kiện  Microcontroller
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nhà sản xuất  ETC2 [List of Unclassifed Manufacturers]
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LM3S1110-IRN50-A1T bảng dữ liệu(HTML) 5 Page - List of Unclassifed Manufacturers

  LM3S1110-IRN50-A1T Datasheet HTML 1Page - List of Unclassifed Manufacturers LM3S1110-IRN50-A1T Datasheet HTML 2Page - List of Unclassifed Manufacturers LM3S1110-IRN50-A1T Datasheet HTML 3Page - List of Unclassifed Manufacturers LM3S1110-IRN50-A1T Datasheet HTML 4Page - List of Unclassifed Manufacturers LM3S1110-IRN50-A1T Datasheet HTML 5Page - List of Unclassifed Manufacturers LM3S1110-IRN50-A1T Datasheet HTML 6Page - List of Unclassifed Manufacturers LM3S1110-IRN50-A1T Datasheet HTML 7Page - List of Unclassifed Manufacturers LM3S1110-IRN50-A1T Datasheet HTML 8Page - List of Unclassifed Manufacturers LM3S1110-IRN50-A1T Datasheet HTML 9Page - List of Unclassifed Manufacturers Next Button
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10
General-Purpose Timers ................................................................................................. 185
10.1
Block Diagram ........................................................................................................................ 186
10.2
Functional Description ............................................................................................................. 186
10.2.1 GPTM Reset Conditions .......................................................................................................... 186
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 186
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 188
10.3
Initialization and Configuration ................................................................................................. 192
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 192
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 193
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 193
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 194
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 194
10.3.6 16-Bit PWM Mode ................................................................................................................... 195
10.4
Register Map .......................................................................................................................... 195
10.5
Register Descriptions .............................................................................................................. 196
11
Watchdog Timer ............................................................................................................... 221
11.1
Block Diagram ........................................................................................................................ 221
11.2
Functional Description ............................................................................................................. 221
11.3
Initialization and Configuration ................................................................................................. 222
11.4
Register Map .......................................................................................................................... 222
11.5
Register Descriptions .............................................................................................................. 223
12
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 244
12.1
Block Diagram ........................................................................................................................ 245
12.2
Functional Description ............................................................................................................. 245
12.2.1 Transmit/Receive Logic ........................................................................................................... 245
12.2.2 Baud-Rate Generation ............................................................................................................. 246
12.2.3 Data Transmission .................................................................................................................. 247
12.2.4 Serial IR (SIR) ......................................................................................................................... 247
12.2.5 FIFO Operation ....................................................................................................................... 248
12.2.6 Interrupts ................................................................................................................................ 248
12.2.7 Loopback Operation ................................................................................................................ 249
12.2.8 IrDA SIR block ........................................................................................................................ 249
12.3
Initialization and Configuration ................................................................................................. 249
12.4
Register Map .......................................................................................................................... 250
12.5
Register Descriptions .............................................................................................................. 251
13
Synchronous Serial Interface (SSI) ................................................................................ 285
13.1
Block Diagram ........................................................................................................................ 285
13.2
Functional Description ............................................................................................................. 285
13.2.1 Bit Rate Generation ................................................................................................................. 286
13.2.2 FIFO Operation ....................................................................................................................... 286
13.2.3 Interrupts ................................................................................................................................ 286
13.2.4 Frame Formats ....................................................................................................................... 287
13.3
Initialization and Configuration ................................................................................................. 294
13.4
Register Map .......................................................................................................................... 295
13.5
Register Descriptions .............................................................................................................. 296
14
Analog Comparators ....................................................................................................... 322
14.1
Block Diagram ........................................................................................................................ 322
5
September 02, 2007
Preliminary
LM3S1110 Microcontroller


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