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ST24 bảng dữ liệu(PDF) 6 Page - STMicroelectronics |
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ST24 bảng dữ liệu(HTML) 6 Page - STMicroelectronics |
6 / 16 page Symbol Alt Parameter Min Max Unit tCH1CH2 tR Clock Rise Time 1 µs tCL1CL2 tF Clock Fall Time 300 ns tDH1DH2 tR Input Rise Time 1 µs tDL1DL1 tF Input Fall Time 300 ns tCHDX (1) tSU:STA Clock High to Input Transition 4.7 µs tCHCL tHIGH Clock Pulse Width High 4 µs tDLCL tHD:STA Input Low to Clock Low (START) 4 µs tCLDX tHD:DAT Clock Low to Input Transition 0 µs tCLCH tLOW Clock Pulse Width Low 4.7 µs tDXCX tSU:DAT Input Transition to Clock Transition 250 ns tCHDH tSU:STO Clock High to Input High (STOP) 4.7 µs tDHDL tBUF Input High to Input Low (Bus Free) 4.7 µs tCLQV (2) tAA Clock Low to Next Data Out Valid 0.3 3.5 µs tCLQX tDH Data Out Hold Time 300 ns fC fSCL Clock Frequency 100 kHz tW (3) tWR Write Time 10 ms Notes: 1. For a reSTART condition, or following a write cycle. 2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP conditions. 3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the maximum programming time is doubled to 20ms. Table 7. AC Characteristics (TA = 0 to 70 °C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V) The 4 most significant bits of the device select code are the device type identifier, corresponding to the I2C bus definition. For these memories the 4 bits are fixed as 1010b. The following 3 bits identify the specific memory on the bus. They are matched to the chip enable signals E2, E1, E0. Thus up to 8 x 1K memories can be connected on the same bus giving a memory capacity total of 8K bits. After a START condition any memory on the bus will iden- tify the device code and compare the following 3 bits to its chip enable inputs E2, E1, E0. The 8th bit sent is the read or write bit (RW), this bit is set to ’1’ for read and ’0’ for write operations. If a match is found, the corresponding memory will acknowledge the identification on the SDA bus during the 9th bit time. DEVICE OPERATION (cont’d) Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.2VCC to 0.8VCC Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC AC MEASUREMENT CONDITIONS AI00825 0.8VCC 0.2VCC 0.7VCC 0.3VCC Figure 4. AC Testing Input Output Waveforms 6/16 ST24/25C01, ST24C01R, ST24/25W01 |
Số phần tương tự - ST24 |
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Mô tả tương tự - ST24 |
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