MOTOROLA CMOS LOGIC DATA

5

MC14527B

Figure 3. Power Dissipation Test Circuit and Waveform

CLOCK

50% DUTY CYCLE

20 ns

20 ns

VDD

VSS

VARIABLE WIDTH

90%

50%

10%

PULSE

GENERATOR

VDD

ID

VDD

VSS

CL

CL

CL

CL

500

pF

0.01

µF

CERAMIC

CASC

Ein

CLOCK

ST

A

B

C

D

Eout

OUT

OUT

“9”

S

CLEAR

LOGIC DIAGRAM

T

C

R

Q

Q

T

C

R

Q

Q

T

C

R

Q

Q

T

C

R

Q

S

S

a

b

c

d

D

C

B

A

3

2

15 14

ENABLE IN

11

9

CLOCK

CLEAR

13

SET TO NINE

4

R1

R4

R2

R3

6 OUT

5 OUT

1 “9”

7 ENABLE OUT

10

12

STROBE CASCADE

VDD = PIN 16

VSS = PIN 8