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STOTG04EQTR bảng dữ liệu(PDF) 8 Page - STMicroelectronics |
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8 / 26 page Electrical characteristics STOTG04E 8/26 Table 7. Switching characteristics Over recommended operating conditions unless otherwise is noted. All the typical values are referred to TA = 25°C, VIF = 1.8V, VBAT = 3.3V, RS = 20Ω, CEXT = 220nF, CT = 4.7µF, and CTRM = 1µF Symbol Parameter Test Conditions Min. Typ. Max. Unit TVBUS_RISE VBUS rise time ILOAD = 8mA, CT = 10µF 1100 ms DIFFERENTIAL DRIVER tR Data signal rise time Full-speed mode, CLOAD = 50pF 48.5 20 ns Low-speed mode, CLOAD = 600pF 75 110 300 tF Data signal rise time Full-speed mode, CLOAD = 50pF 48.5 20 ns Low-speed mode, CLOAD = 600pF 75 110 300 tP_DRV_R Propagation delay of the driver, rising edge; DAT_SE0 mode Full-speed mode, CLOAD = 50pF 38 ns Low-speed mode, CLOAD = 600pF 280 Propagation delay of the driver, rising edge; VP_VM mode Full-speed mode, CLOAD = 50pF 55 ns Low-speed mode, CLOAD = 600pF 300 tP_DRV_F Propagation delay of the driver, falling edge; DAT_SE0 mode Full-speed mode, CLOAD = 50pF 38 ns Low-speed mode, CLOAD = 600pF 280 Propagation delay of the driver, rising edge; VP_VM mode Full-speed mode, CLOAD = 50pF 55 ns Low-speed mode, CLOAD = 600pF 300 tRFM Rise and fall time matching (tR/ tF) excluding the first transition from the idle state Full-speed mode 90 111.11 % Low-speed mode 80 125 SINGLE-ENDED RECEIVERS tP_SE_R Propagation delay of the SE receiver, rising edge Full-speed mode, input slope 15ns 18 ns Low-speed mode, input slope 150ns 18 tP_SE_F Propagation delay of the SE receiver, falling edge Full-speed mode, input slope 15ns 18 ns Low-speed mode, input slope 150ns 18 DIFFERENTIAL RECEIVER tP_DIF_R Propagation delay of the SE receiver, rising edge Full-speed mode, input slope 15ns 24 ns Low-speed mode, input slope 150ns 24 tP_DIF_F Propagation delay of the SE receiver, falling edge Full-speed mode, input slope 15ns 24 ns Low-speed mode, input slope 150ns 24 DIGITAL INTERFACE tSET_OE Output enable setup time 50 ns tTA_OI Output to input bus turnaround time (1, 2) 05 ns tTA_IO Output to input bus turnaround time (1, 2) 05 ns I2C BUS (3) fSCL SCL clock frequency 100 kHz tLOW Low period of the SCL clock 4.7 µs tHIGH High period of the SCL clock 4.0 µs tIICR Rise time of both SDA and SCL signals 1000 ns |
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