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ADS8512IDW bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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ADS8512IDW bảng dữ liệu(HTML) 11 Page - Texas Instruments |
11 / 32 page BASIC OPERATION INTERNAL DATACLK 1 2 3 4 5 6 7 8 R1 IN GND R2 IN R3 IN BUF CAP REF GND V S PWRD BUSY CS CONV EXT/INT DATA DATACLK 16 15 14 13 12 11 10 9 ADS8512 ±10V +5V C 3 1µF C 4 0.01µF C 1 0.1µF C 2 10µF C 5 1µF + + ConvertPulse 40nsmin + FrameSync(optional) EXTERNAL DATACLK 1 2 3 4 5 6 7 8 R1 IN GND R2 IN R3 IN BUF CAP REF GND V S PWRD BUSY CS CONV EXT/INT DATA DATACLK 16 15 14 13 12 11 10 9 ADS8512 ±10V NOTE:(1) Tie toGNDiftheoutputswillalwaysbeactive. CS +5V +5V C 1 0.1µF C 2 10µF C 5 1µF + ConvertPulse 40nsmin + Interrupt(optional) ExternalClock ChipSelect(optional(1)) C 3 1µF C 4 0.01µF + ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 Figure 36 shows a basic circuit to operate the ADS8512 with a ±10-V input range. To begin a conversion and serial transmission of the results from the previous conversion, a falling edge must be provided to the CONV input. BUSY goes low to indicate that a conversion has started, and stays low until the conversion is complete. During the conversion, the results of the previous conversion are transmitted via DATA while DATACLK provides the synchronous clock for the serial data. The data format is 12-bit, binary twos complement, MSB first. Each data bit is valid on both the rising and falling edge of DATACLK. BUSY is low during the entire serial transmission and can be used as a frame synchronization signal. Figure 36. Basic Operating Circuit, ±10-V Input Range, Internal DATACLK Figure 37 shows another basic circuit to operate the ADS8512 with a ±10-V input range. To begin a conversion, a falling edge must be provided to the CONV input. BUSY goes low to indicate that a conversion has started and stays low until the conversion is complete. Just before BUSY rises near the end of the conversion, the conversion result held in the internal working register is transferred to the internal shift register. The internal shift register is clocked via the DATACLK input. The recommended method of reading the conversion result is to provide the serial clock after the conversion has completed. See the External DATACLK subsection under the Reading Data section of this data sheet for more information. Figure 37. Basic Operating Circuit, ±10-V Input Range, External DATACLK Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS8512 |
Số phần tương tự - ADS8512IDW |
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Mô tả tương tự - ADS8512IDW |
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