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MC74LCX373 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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MC74LCX373 bảng dữ liệu(HTML) 1 Page - ON Semiconductor |
1 / 9 page ![]() © Semiconductor Components Industries, LLC, 2007 November, 2007 - Rev. 8 1 Publication Order Number: MC74LCX373/D MC74LCX373 Low-Voltage CMOS Octal Transparent Latch With 5 V-Tolerant Inputs and Outputs (3-State, Non-Inverting) The MC74LCX373 is a high performance, non-inverting octal transparent latch operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX373 inputs to be safely driven from 5 V devices. The MC74LCX373 contains 8 D-type latches with 3-state outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. Features • Designed for 2.3 to 3.6 V VCC Operation • 5 V Tolerant - Interface Capability With 5 V TTL Logic • Supports Live Insertion and Withdrawal • IOFF Specification Guarantees High Impedance When VCC = 0 V • LVTTL Compatible • LVCMOS Compatible • 24 mA Balanced Output Sink and Source Capability • Near Zero Static Supply Current in all Three Logic States (10 mA) Substantially Reduces System Power Requirements • Latchup Performance Exceeds 500 mA • ESD Performance: Human Body Model >2000 V Machine Model >200 V • Pb-Free Packages are Available* *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 20 1 1 20 MARKING DIAGRAMS A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb-Free Package SOIC-20 DW SUFFIX CASE 751D LCX373 AWLYYWWG LCX 373 ALYW G G TSSOP-20 DT SUFFIX CASE 948E SOEIAJ-20 M SUFFIX CASE 967 74LCX373 AWLYWWG 1 1 1 20 1 20 20 20 See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ORDERING INFORMATION http://onsemi.com (Note: Microdot may be in either location) |
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