Advanced Clock Drivers Device Data

Freescale Semiconductor

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MC88LV926

Figure 5. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships

Figure 6. Output/Input Switching Waveforms and Timing Relationships

4.

0

°C to 70°C and the full V

the

ΔT and ΔV

5.

Therefore an external pull–up resistor must be provide

impedance state (after the MC88LV926 is phase-locked

2X_Q

Q0

Q1

Q2

Q3

QCLKEN

RST_OUT

SYNC

MR

PLL_EN

RST_IN

12.5 MHz

Crystal

Oscillator

66 MHz P–Clock

Output

33 MHz

B–Clock

and System

Outputs

Delay 33 MHz CLKEN Output

SYNC Input

Q0–Q3 Outputs

2X_Q Output

QCLKEN

NOTES:

1.

The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a

50% duty cycle.

2.

as “windows”, not as a ± deviation around a center point.

MC88LV926

Low Skew CMOS PLL 68060 Clock Driver

NETCOM

IDT™ Low Skew CMOS PLL 68060 Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC88LV926

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