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MC88LV926 bảng dữ liệu(PDF) 7 Page - Integrated Device Technology |
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MC88LV926 bảng dữ liệu(HTML) 7 Page - Integrated Device Technology |
7 / 11 page Advanced Clock Drivers Device Data Freescale Semiconductor 7 MC88LV926 Figure 5. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships Figure 6. Output/Input Switching Waveforms and Timing Relationships 4. The tPD spec includes the full temperature range from 0 °C to 70°C and the full V CC range from 3.0 V to 3.3 V. If the ΔT and ΔV CC is a given system are less than the specification limits, the tPD spec window will be reduced. 5. The RST_OUT pin is an open drain N–Channel output. Therefore an external pull–up resistor must be provide to pull up the RST_OUT pin when it goes into the high impedance state (after the MC88LV926 is phase-locked to the reference input with RST_IN held high or 1024 ‘Q' cycles after the RST_IN pin goes high when the part is locked). In the tPLZ and tPZL specifications, a 1 KΩ resistor is used as a pull-up as shown in Figure 3. 2X_Q Q0 Q1 Q2 Q3 QCLKEN RST_OUT SYNC MR PLL_EN RST_IN 12.5 MHz Crystal Oscillator 66 MHz P–Clock Output 33 MHz B–Clock and System Outputs Delay 33 MHz CLKEN Output SYNC Input Q0–Q3 Outputs 2X_Q Output QCLKEN tCYCLE SYNC Input tSKEWall tSKEWf tSKEWr tSKEWf tSKEWr tCYCLE ‘Q' Outputs tSKEWQCLKEN tSKEWQCLKEN NOTES: 1. The MC88LV926 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as “windows”, not as a ± deviation around a center point. MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM IDT™ Low Skew CMOS PLL 68060 Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC88LV926 7 |
Số phần tương tự - MC88LV926 |
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Mô tả tương tự - MC88LV926 |
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