MC88LV926 datasheet(5/11 Pages) IDT

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Advanced Clock Drivers Device Data

Freescale Semiconductor

5

MC88LV926

NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked condition.

Table 6. Frequency Specifications (TA = 0°C to 70°C; VCC = 3.3 V ± 0.3 V

Symbol

Parameter

Guaranteed Minimum

Unit

Fmax (2X_Q)

Maximum Operating Frequency, 2X_Q Output

66

MHz

Fmax (‘Q')

Maximum Operating Frequency,

Q0–Q3 Outputs

33

MHz

Table 7. AC Characteristics (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V

Symbol

Parameter

Minimum

Maximum

Unit

Condition

tRISE/FALL

All Outputs

Rise/Fall Time, into 50

Ω Load

0.3

1.6

ns

tRISE – 0.8 V to 2.0 V

tFALL – 2.0 V to 0.8 V

tRISE/FALL

2X_Q Output

Rise/Fall Time into a 50

Ω Load

0.5

1.6

ns

tRISE – 0.8 V to 2.0 V

tFALL – 2.0 V to 0.8 V

tpulse width(a)

(1)

(Q0, Q1, Q2, Q3)

1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this

methodology.

Output Pulse Width

Q0, Q1, Q2, Q3 at 1.65V

0.5tcycle – 0.5

0.5tcycle + 0.5

ns

50

Ω Load Terminated to V

CC/

2 (See Application Note 3)

tpulse width(b)

(1)

(2X_Q Output)

Output Pulse Width

2X_Q at 1.65V

0.5tcycle – 0.5

0.5tcycle + 0.5

ns

50

Ω Load Terminated to V

CC/

2 (See Application Note 3)

tSKEWr

(2)

(Rising)

2. Under equally loaded conditions and at a fixed temperature and voltage.

Output–to–Output Skew

Between Outputs Q0–Q2

(Rising Edge Only)

–500

ps

Into a 50

Ω Load Terminated to

VCC/2 (See Timing Diagram in

Figure 6)

tSKEWf

(2)

(Falling)

Output–to–Output Skew

Between Outputs Q0–Q2

(Falling Edge Only)

–1.0

ns

Into a 50

Ω Load Terminated to

VCC/2 (See Timing Diagram in

Figure 6)

tSKEWall

(2)

Output–to–Output Skew

2X_Q, Q0–Q2, Q3

–750

ps

Into a 50

Ω Load Terminated to

VCC/2 (See Timing Diagram in

Figure 6)

tSKEW QCLKEN

(1)

(2)

Output–to–Output Skew

QCLKEN to 2X_Q

2X_Q = 50 MHz

2X_Q = 66 MHz

9.7(3)

7.0(3)

3. Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060.

–

ns

Into a 50

Ω Load Terminated to

VCC/2 (See Timing Diagram in

Figure 6)

tLOCK

(4)

4. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1 μF; tLOCK Min is with C1 = 0.01 μF.

Phase–Lock Acquisition Time,

All Outputs to SYNC Input

110

ms

tPHL MR – Q

(1)

Propagation Delay,

MR to Any Output (High–Low)

1.5

13.5

ns

Into a 50

Ω Load

Terminated to VCC/2

tREC, MR to

SYNC(1)(5)

5. Specification is valid only when the PLL_EN pin is low.

Reset Recovery Time rising MR edge to

falling SYNC edge(6)

6. See Application Notes, Note 4 for the distribution in time of each output referenced to SYNC.

9–

ns

tW, MR LOW

(1) (5)

Minimum Pulse Width, MR input Low

5–

ns

tW, RST_IN

LOW(1)

Minimum Pulse Width, RST_IN Low

10

–

ns

When in Phase–Lock

tPZL

(1)

Output Enable Time

RST_IN Low to RST_OUT Low

1.5

16.5

ns

See Application Notes, Note 5

tPLZ

(1)

Output Enable Time

RST_IN High to RST_OUT High Z

1016 ‘Q' Cycles

(508 Q/2 Cycles)

1024 ‘Q' Cycles

(512 Q/2 Cycles)

ns

See Application Notes, Note 5

MC88LV926

Low Skew CMOS PLL 68060 Clock Driver

NETCOM

IDT™ Low Skew CMOS PLL 68060 Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC88LV926

5

Số phần tương tự - MC88LV926

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