TIMING CHARACTERISTICS for Figure 2 and Figure 3

(1) (2) (3)

DAC9881

At –40

°C to +85°C, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

MAX

UNIT

2.7

20

MHz

Maximum clock frequency

3.6

25

MHz

2.7

50

ns

Minumum CS high time

3.6

30

ns

2.7

10

ns

CS falling edge to SCLK rising edge

3.6

8

ns

2.7

10

ns

SCLK falling edge to CS falling edge setup

time

3.6

10

ns

2.7

25

ns

SCLK low time

3.6

20

ns

2.7

25

ns

SCLK high time

3.6

20

ns

2.7

50

ns

SCLK cycle time

3.6

40

ns

2.7

10

ns

SCLK rising edge to CS rising edge

3.6

10

ns

2.7

5

ns

Input data setup time

3.6

5

ns

2.7

5

ns

Input data hold time

3.6

5

ns

2.7

15

ns

SDO active from CS falling edge

3.6

10

ns

2.7

20

ns

SDO data valid from SCLK falling edge

3.6

15

ns

2.7

25

ns

SDO data hold from SCLK rising edge

3.6

20

ns

2.7

8

ns

SDO High-Z from CS rising edge

3.6

5

ns

2.7

10

ns

CS rising edge to LDAC falling edge

3.6

5

ns

2.7

15

ns

LDAC pulse width

3.6

10

ns

(1)

(2)

Ensured by design. Not production tested.

(3)

Sample tested during the initial release and after any redesign or process changes that may affect these parameters.

10

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