MV20556

MOSEL VITELIC INC.

2/27

PID256** 07/97

Specifications subject to change without notice, contact your sales representatives for the most recent information.

Preliminary

Block Diagram

RES

Vdd

Vss

XTAL2

XTAL1

Timer 1

Timer 0

Decoder &

Register

128 bytes

RAM

4K bytes

ROM

Register

Program

Counter

PC

Increamenter

Buffer

DPTR

Stack

Pointer

Port 3

Latch

Port 1

Latch

Port 1

Driver

Port 3

Driver

7

8

Reset

Circuit

Power

Circuit

Interrupt

Circuit

Timming

Generator

to pertinent blocks

to whole chip

to pertinent blocks

to whole system

128

bits

SFR

includes

Acc &

PSW,

etc.

Buffer1

Buffer2

ALU