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M74HC107B1R bảng dữ liệu(PDF) 1 Page - STMicroelectronics |
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1 / 11 page M54HC107 M74HC107 October 1992 DUAL J-K FLIP FLOP WITH CLEAR B1R (Plastic Package) ORDER CODES : M54HC107F1R M74HC107M1R M74HC107B1R M74HC107C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection INPUT AND OUTPUT EQUIVALENT CIRCUIT . HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC =5 V . LOW POWER DISSIPATION ICC =2 µA (MAX.) AT TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE IOH =IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS107 The M54/74HC107 is a high speed CMOS DUAL J- K FLIP FLOP fabricated in silicon gate C 2MOS tech- nology. It has the same high speed performance of LSTTL combined with true CMOS low power con- sumption. These flip-flop are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has inde- pendent J, K, CLOCK, and CLEAR input and Q and Q outputs. CLEAR is independent of the clock and accomplished by a logic low on the input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. DESCRIPTION 1/11 |
Số phần tương tự - M74HC107B1R |
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Mô tả tương tự - M74HC107B1R |
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