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M40SZ100WMH bảng dữ liệu(PDF) 11 Page - STMicroelectronics

tên linh kiện M40SZ100WMH
Giải thích chi tiết về linh kiện  5V or 3V NVRAM SUPERVISOR FOR LPSRAM
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M40SZ100Y, M40SZ100W
Power-on Reset Output
All microprocessors have a reset input which forc-
es them to a known state when starting. The
M40SZ100Y/W has a reset output (RST) pin which
is guaranteed to be low by VPFD (see Table 5,
page 7). This signal is an open drain configuration.
An appropriate pull-up resistor to VCC should be
chosen to control the rise time. This signal will be
valid for all voltage conditions, even when VCC
equals VSS (with valid battery voltage).
Once VCC exceeds the power failure detect volt-
age VPFD, an internal timer keeps RST low for
tREC to allow the power supply to stabilize.
Reset Input (RSTIN)
The M40SZ100Y/W provides one independent in-
put which can generate an output reset. The dura-
tion and function of this reset is identical to a reset
generated by a power cycle. Table 7 and Figure 12
illustrate the AC reset characteristics of this func-
tion. Pulses shorter than tRLRH will not generate a
reset condition. RSTIN is internally pulled up to
VCC through a 100kΩ resistor.
Figure 12. RSTIN Timing Waveform
Note: With pull-up resistor
Table 7. Reset AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. CL = 5pF (see Figure 8, page 6).
Symbol
Parameter(1)
Min
Max
Unit
tRLRH
(2)
RSTIN Low to RSTIN High
200
ns
tR1HRH
(3)
RSTIN High to RST High
40
200
ms
AI04768
RST
(1)
RSTIN
tRLRH
tR1HRH


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