Data Sheet #: TM084
Page 8 of 44
Rev: P02
Date: 12/5/06
© Copyright 200
6 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC4130
Synchronous Clock for SETS
Data Sheet
0x45
T4_Short_Term_Accu_History
31-0
R
Short term Accumulated History for T4 relative to the TCXO
0x49
T4_User_Accu_History
31-0
R/W
User Holdover data for T4 relative to the TCXO
0x4d
T4_HO_BW_Ramp
7-0
R/W
Bits7-4, Long term history accumuation bandwidth: 9.7, 4.9, 2.4, 1.2,
0.61, 0.03 mHz
Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62,
0.31 mHz
Bit21:0, Ramp control: none, 1, 1.5, 2 ppm/S
0x4e
T4_Priority_Table
47-0
R/W
REF1-12 selection priority for automatic mode, 4 bits/reference
0x54
T4_PLL_Status
7-0
R
LTH Avail, LTH Complete, OOP, LOL, LOS, Sync
0x55
T4_Accu_Flush
0-0
W
0: Flush current history, 1: Flush all histories
0x56
CLK0_Sel
0-0
R/W
155.52 MHz clock enable/disable for CLK0
0x57
CLK1_Sel
1-0
R/W
19.44MHz/38.88MHz/77.76MHz or disable select for CLK1
0x58
CLK2_Sel
1-0
R/W
19.44MHz/38.88MHz/77.76MHz or disable select for CLK2
0x59
CLK3_Sel
5-0
R/W
8KHz output 50% duty cycle or pulse width selection for CLK3
0x5a
CLK4_Sel
5-0
R/W
2KHz output 50% duty cycle or pulse width selection for CLK4
0x5b
CLK5_Sel
1-0
R/W
DS3/E3 select for CLK5
0x5c
CLK6_Sel
3-0
R/W
DS1 x n / E1 x n selector for CLK6
0x5d
CLK7_Sel
1-0
R/W
Ds1/E1 selector for CLK7
0x5e
Intr_Event
9-0
R/W
Interrupt event
0x60
Intr_Enable
9-0
R/W
Interrupt enable
Table 4: Register Map
Addr
Reg Name
Bits
Type
Description
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