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M27512-3F1 bảng dữ liệu(PDF) 8 Page - STMicroelectronics |
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M27512-3F1 bảng dữ liệu(HTML) 8 Page - STMicroelectronics |
8 / 11 page AI00774B n = 1 Last Addr VERIFY E = 1ms Pulse ++n > 25 ++ Addr VCC = 6V, VPP = 12.5V FAIL CHECK ALL BYTES VCC = 5V, VPP = 5V YES NO YES NO YES NO E = 3ms Pulse by n Figure 8. Fast Programming Flowchart AI00773B n = 0 Last Addr VERIFY E = 500 µs Pulse ++n = 25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL BYTES VCC = 5V, VPP = 5V YES NO YES NO YES NO SET MARGIN MODE RESET MARGIN MODE Figure 9. PRESTO Programming Flowchart DEVICE OPERATION (cont’d) The Fast Programming Algorithm utilizes two differ- ent pulse types : initial and overprogram. The du- ration of the initial E pulse(s) is 1ms, which will then be followed by a longer overprogram pulse of length 3ms by n (n is an iteration counter and is equal to the number of the initial one millisecond pulses applied to a particular M27512 location), before a correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the over program pulse is applied. The entire sequence of program pulses is per- formed at VCC = 6V and GVPP = 12.5V (byte verifi- cations at VCC = 6V and GVPP = VIL). When the Fast Programming cycle has been completed, all bytes should be compared to the original data with VCC = 5V. PRESTO Programming Algorithm PRESTO Programming Algorithm allows to pro- gram the whole array with a guaranted margin, in a typical time of less than 50 seconds (to be com- pared with 283 seconds for the Fast algorithm). This can be achieved with the STMicroelectronics M27512 due to several design innovations de- scribed in the next paragraph that improves pro- gramming efficiency and brings adequate margin for reliability. Before starting the programming the internal MARGIN MODE circuit is set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 500 µs program pulses are applied to each byte until a correct verify occurs. No overprogram pulses are applied since the verify in MARGIN MODE provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27512s in parallel with different data is also easily accomplished. Except for E, all like inputs (including GVPP) of the parallel M27512 may be common. A TTL low level pulse applied to a M27512’s E input, with GVpp at 12.5V, will program that M27512. A high level E input inhibits the other M27512s from being pro- grammed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correctly programmed. The verify is accomplished with GVpp and E at VIL. Data should be verified tDV after the falling edge of E. M27512 8/11 |
Số phần tương tự - M27512-3F1 |
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Mô tả tương tự - M27512-3F1 |
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