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M27256-20F1 bảng dữ liệu(PDF) 7 Page - STMicroelectronics |
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M27256-20F1 bảng dữ liệu(HTML) 7 Page - STMicroelectronics |
7 / 10 page tAVPL VALID AI00779 A0-A12 Q0-Q7 VPP VCC P G DATA IN DATA OUT E tQVPL tVPHPL tVCHPL tPHQX tPLPH tGLQV tQXGL tELPL tGHQZ tGHAX PROGRAM VERIFY Figure 6. Programming and Verify Modes AC Waveforms AI00775B n = 1 Last Addr VERIFY P = 1ms Pulse ++n > 25 ++ Addr VCC = 6V, VPP = 12.5V FAIL CHECK ALL BYTES VCC = 5V, VPP 5V YES NO YES NO YES NO P = 3ms Pulse by n Figure 7. Fast Programming Flowchart been successfully programmed. A flowchart of the M2764A Fast Programming Algorithm is shown on the last page. The Fast Programming Algorithm utilizes two different pulse types: initial and over- program. The duration of the initial P pulse(s) is 1ms, which will then be followed by a longer overprogram pulse of length 3ms by n (n is equal to the number of the initial one millisecond pulses applied to a particular M2764A location), before a correct verify occurs. Up to 25 one-millisecond pulses per byte are pro- vided for before the overprogram pulse is applied. The entire sequence of program pulses and byte verifications is performed at VCC = 6V and VPP = 12.5V. When the Fast Programming cycle has been completed, all bytes should be compared to the original data with VCC = 5V and VPP = 5V. Program Inhibit Programming of multiple M2764A in parallel with different data is also easily accomplished. Except for E, all like inputs (including G) of the parallel M2764A may be common. A TTL low pulse applied to a M2764A’s E input, with VPP at 12.5V, will program that M2764A. A high level E input inhibits the other M2764As from being programmed. DEVICE OPERATION (cont’d) 7/10 M2764A |
Số phần tương tự - M27256-20F1 |
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Mô tả tương tự - M27256-20F1 |
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