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STK14EC16-BF25I bảng dữ liệu(PDF) 7 Page - Simtek Corporation |
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STK14EC16-BF25I bảng dữ liệu(HTML) 7 Page - Simtek Corporation |
7 / 21 page STK14EC16 7 Simtek Confidential Jan, 2008 Document Control #ML0061 Rev 1.1 Preliminary SRAM WRITE CYCLES #1, #2, and #3 Note g: If W is low when E goes low, the outputs remain in the high-impedance state. Note h: E or W must be ≥ V IH during address transitions. SRAM WRITE CYCLE #1: W Controlledg,h SRAM WRITE CYCLE #2: E Controlledg,h NO. SYMBOLS PARAMETER STK14EC16-15 STK14EC16-25 STK14EC16-45 UNITS #1 #2 #3 Alt. MIN MAX MIN MAX MIN MAX 15 tAVAV tAVAV tAVAV tWC Write Cycle Time 15 25 45 ns 16 tWLWH tWLEH tWLBH tWP Write Pulse Width 10 20 30 ns 17 tELWH tELEH tELBH tCW Chip Enable to End of Write 15 20 30 ns 18 tBLWH tBLEH tBLBH Byte Enable to End of Write 15 20 30 ns 19 tDVWH tDVEH tDVBH tDW Data Set-up to End of Write 5 10 15 ns 20 tWHDX tEHDX tBHDX tDH Data Hold after End of Write 0 0 0 ns 21 tAVWH tAVEH tAVBH tAW Address Set-up to End of Write 10 20 30 ns 22 tAVWL tAVEL tAVBL tAS Address Set-up to Start of Write 0 0 0 ns 23 tWHAX tEHAX tBHAX tWR Address Hold after End of Write 0 0 0 ns 24 tWLQZ e, g tWZ Write Enable to Output Disable 7 10 15 ns 25 tWHQX tOW Output Active after End of Write 3 3 3 ns Address Valid High Impedance Input Data Valid Previous Data tAVAV (15) tELWH (17) tBLWH (18) tAVWH (21) tWLWH (16) Address Data Output Data Input E LB, UB W tAVWL (22) tWLQZ (24) tDVWH (19) tWHQX (25) tWHDX (20) tWHAX (23) Input Data Valid High Impedance Address Valid Data Input Data Output LB , UB W E Address tAVAV (15) tAVWL (22) tELEH (17) tEHAX (23) tBLEH (18) tWLEH (16) tEHDX (20) tDVEH (19) |
Số phần tương tự - STK14EC16-BF25I |
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Mô tả tương tự - STK14EC16-BF25I |
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