10.2
Functional Description ............................................................................................................. 196
10.2.1 GPTM Reset Conditions .......................................................................................................... 196
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 196
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 198
10.3
Initialization and Configuration ................................................................................................. 202
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 202
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 203
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 203
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 204
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 204
10.3.6 16-Bit PWM Mode ................................................................................................................... 205
10.4
Register Map .......................................................................................................................... 205
10.5
Register Descriptions .............................................................................................................. 206
11
Watchdog Timer ............................................................................................................... 228
11.1
Block Diagram ........................................................................................................................ 228
11.2
Functional Description ............................................................................................................. 228
11.3
Initialization and Configuration ................................................................................................. 229
11.4
Register Map .......................................................................................................................... 229
11.5
Register Descriptions .............................................................................................................. 230
12
UART ................................................................................................................................. 251
12.1
Block Diagram ........................................................................................................................ 252
12.2
Functional Description ............................................................................................................. 252
12.2.1 Transmit/Receive Logic ........................................................................................................... 252
12.2.2 Baud-Rate Generation ............................................................................................................. 253
12.2.3 Data Transmission .................................................................................................................. 254
12.2.4 Serial IR (SIR) ......................................................................................................................... 254
12.2.5 FIFO Operation ....................................................................................................................... 255
12.2.6 Interrupts ................................................................................................................................ 255
12.2.7 Loopback Operation ................................................................................................................ 256
12.2.8 IrDA SIR block ........................................................................................................................ 256
12.3
Initialization and Configuration ................................................................................................. 256
12.4
Register Map .......................................................................................................................... 257
12.5
Register Descriptions .............................................................................................................. 258
13
SSI ..................................................................................................................................... 291
13.1
Block Diagram ........................................................................................................................ 291
13.2
Functional Description ............................................................................................................. 292
13.2.1 Bit Rate Generation ................................................................................................................. 292
13.2.2 FIFO Operation ....................................................................................................................... 292
13.2.3 Interrupts ................................................................................................................................ 292
13.2.4 Frame Formats ....................................................................................................................... 293
13.3
Initialization and Configuration ................................................................................................. 300
13.4
Register Map .......................................................................................................................... 301
13.5
Register Descriptions .............................................................................................................. 302
14
Inter-Integrated Circuit (I
2C) Interface ............................................................................ 326
14.1
Block Diagram ........................................................................................................................ 326
14.2
Functional Description ............................................................................................................. 326
14.2.1 I
2C Bus Functional Overview .................................................................................................... 327
5
June 14, 2007
Luminary Micro Confidential-Advance Product Information
LM3S1150 Microcontroller
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