10
General-Purpose Timers ................................................................................................. 197
10.1
Block Diagram ........................................................................................................................ 198
10.2
Functional Description ............................................................................................................. 198
10.2.1 GPTM Reset Conditions .......................................................................................................... 198
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 198
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 200
10.3
Initialization and Configuration ................................................................................................. 204
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 204
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 205
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 205
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 206
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 206
10.3.6 16-Bit PWM Mode ................................................................................................................... 207
10.4
Register Map .......................................................................................................................... 207
10.5
Register Descriptions .............................................................................................................. 208
11
Watchdog Timer ............................................................................................................... 233
11.1
Block Diagram ........................................................................................................................ 233
11.2
Functional Description ............................................................................................................. 233
11.3
Initialization and Configuration ................................................................................................. 234
11.4
Register Map .......................................................................................................................... 234
11.5
Register Descriptions .............................................................................................................. 235
12
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 256
12.1
Block Diagram ........................................................................................................................ 257
12.2
Functional Description ............................................................................................................. 257
12.2.1 Transmit/Receive Logic ........................................................................................................... 257
12.2.2 Baud-Rate Generation ............................................................................................................. 258
12.2.3 Data Transmission .................................................................................................................. 259
12.2.4 Serial IR (SIR) ......................................................................................................................... 259
12.2.5 FIFO Operation ....................................................................................................................... 260
12.2.6 Interrupts ................................................................................................................................ 260
12.2.7 Loopback Operation ................................................................................................................ 261
12.2.8 IrDA SIR block ........................................................................................................................ 261
12.3
Initialization and Configuration ................................................................................................. 261
12.4
Register Map .......................................................................................................................... 262
12.5
Register Descriptions .............................................................................................................. 263
13
Synchronous Serial Interface (SSI) ................................................................................ 297
13.1
Block Diagram ........................................................................................................................ 297
13.2
Functional Description ............................................................................................................. 297
13.2.1 Bit Rate Generation ................................................................................................................. 298
13.2.2 FIFO Operation ....................................................................................................................... 298
13.2.3 Interrupts ................................................................................................................................ 298
13.2.4 Frame Formats ....................................................................................................................... 299
13.3
Initialization and Configuration ................................................................................................. 306
13.4
Register Map .......................................................................................................................... 307
13.5
Register Descriptions .............................................................................................................. 308
14
Inter-Integrated Circuit (I
2C) Interface ............................................................................ 334
14.1
Block Diagram ........................................................................................................................ 334
5
September 02, 2007
Preliminary
LM3S1620 Microcontroller
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