Figure 15-1.
Analog Comparator Module Block Diagram ..................................................................... 362
Figure 15-2.
Structure of Comparator Unit .......................................................................................... 363
Figure 15-3.
Comparator Internal Reference Structure ........................................................................ 364
Figure 16-1.
PWM Module Block Diagram .......................................................................................... 374
Figure 16-2.
PWM Count-Down Mode ................................................................................................ 375
Figure 16-3.
PWM Count-Up/Down Mode .......................................................................................... 376
Figure 16-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 376
Figure 16-5.
PWM Dead-Band Generator ........................................................................................... 377
Figure 17-1.
QEI Block Diagram ........................................................................................................ 406
Figure 17-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 407
Figure 18-1.
Pin Connection Diagram ................................................................................................ 422
Figure 21-1.
Load Conditions ............................................................................................................ 440
Figure 21-2.
I
2C Timing ..................................................................................................................... 442
Figure 21-3.
Hibernation Module Timing ............................................................................................. 442
Figure 21-4.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 443
Figure 21-5.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 443
Figure 21-6.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 444
Figure 21-7.
JTAG Test Clock Input Timing ......................................................................................... 445
Figure 21-8.
JTAG Test Access Port (TAP) Timing .............................................................................. 445
Figure 21-9.
JTAG TRST Timing ........................................................................................................ 445
Figure 21-10. External Reset Timing (RST) ........................................................................................... 446
Figure 21-11. Power-On Reset Timing ................................................................................................. 447
Figure 21-12. Brown-Out Reset Timing ................................................................................................ 447
Figure 21-13. Software Reset Timing ................................................................................................... 447
Figure 21-14. Watchdog Reset Timing ................................................................................................. 447
Figure 22-1.
100-Pin LQFP Package .................................................................................................. 448
9
June 14, 2007
Luminary Micro Confidential-Advance Product Information
LM3S1150 Microcontroller