Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 378
Figure 15-13. Slave Command Sequence ............................................................................................ 379
Figure 16-1.
Analog Comparator Module Block Diagram ..................................................................... 404
Figure 16-2.
Structure of Comparator Unit .......................................................................................... 405
Figure 16-3.
Comparator Internal Reference Structure ........................................................................ 406
Figure 17-1.
Pin Connection Diagram ................................................................................................ 416
Figure 20-1.
Load Conditions ............................................................................................................ 434
Figure 20-2.
I
2C Timing ..................................................................................................................... 436
Figure 20-3.
Hibernation Module Timing ............................................................................................. 437
Figure 20-4.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 438
Figure 20-5.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 438
Figure 20-6.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 439
Figure 20-7.
JTAG Test Clock Input Timing ......................................................................................... 440
Figure 20-8.
JTAG Test Access Port (TAP) Timing .............................................................................. 440
Figure 20-9.
JTAG TRST Timing ........................................................................................................ 440
Figure 20-10. External Reset Timing (RST) .......................................................................................... 441
Figure 20-11. Power-On Reset Timing ................................................................................................. 442
Figure 20-12. Brown-Out Reset Timing ................................................................................................ 442
Figure 20-13. Software Reset Timing ................................................................................................... 442
Figure 20-14. Watchdog Reset Timing ................................................................................................. 442
Figure 21-1.
100-Pin LQFP Package .................................................................................................. 443
9
September 02, 2007
Preliminary
LM3S1138 Microcontroller