công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MCF52230 bảng dữ liệu(PDF) 9 Page - Freescale Semiconductor, Inc |
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MCF52230 bảng dữ liệu(HTML) 9 Page - Freescale Semiconductor, Inc |
9 / 48 page MCF52235 Family Configurations MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0 Preliminary Freescale Semiconductor 9 • DMA Controller — Four fully programmable channels — Dual-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 X 32-bit) burst transfers — Source/destination address pointers that can increment or remain constant — 24-bit byte transfer counter per channel — Auto-alignment transfers supported for efficient block movement — Bursting and cycle steal support — support for channel-to-channel linking — Software-programmable DMA channel selections in the UARTs (3) and 32-bit timers (4) •Reset — Separate reset in and reset out signals — Seven sources of reset: – Power-on reset (POR) – External – Software – Watchdog – Loss of clock – Loss of lock – Low-voltage detection (LVD) — Status flag indication of source of last reset • Chip Integration Module (CIM) — System configuration during reset — Selects one of six clock modes — Configures output pad drive strength — Unique part identification number and part revision number • General Purpose I/O interface — Up to 73 bits of general purpose I/O — Bit manipulation supported via set/clear functions — Unused peripheral pins may be used as extra GPIO • JTAG support for system level board testing 1.2.2 V2 Core Overview The Version 2 ColdFire processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds |
Số phần tương tự - MCF52230 |
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Mô tả tương tự - MCF52230 |
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