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MCF52231 bảng dữ liệu(PDF) 11 Page - Freescale Semiconductor, Inc |
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MCF52231 bảng dữ liệu(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 48 page  MCF52235 Family Configurations MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0 Preliminary Freescale Semiconductor 11 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic. The MCF52235 implementation can do the following: • Perform boundary-scan operations to test circuit board electrical continuity • Sample MCF52235 system pins during operation and transparently shift out the result in the boundary scan register • Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan register to a single bit • Disable the output drive to pins during circuit-board testing • Drive output pins to stable levels 1.2.5 On-Chip Memories 1.2.5.1 SRAM The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. 1.2.5.2 Flash The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays to generate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable and programmable, non-volatile program and data memory. The Flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller which supports address speculation and interleaved accesses from the 2-cycle Flash arrays for improved performance. For operation at reduced core frequencies, the access time can be decreased (under program control) to a single-cycle access. A backdoor mapping of the Flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial Flash programming interface that allows the Flash to be read, erased and programmed by an external controller in a format compatible with most SPI bus Flash memory chips. This allows easy device programming via Automated Test Equipment or bulk programming tools. |
Số phần tương tự - MCF52231 |
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Mô tả tương tự - MCF52231 |
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