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MCF52231 bảng dữ liệu(PDF) 10 Page - Freescale Semiconductor, Inc |
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MCF52231 bảng dữ liệu(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 48 page MCF52235 ColdFire® Microcontroller Data Sheet, Rev. 0 Preliminary MCF52235 Family Configurations Freescale Semiconductor 10 prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire Instruction Set Architecture Revision A+ (see the ColdFire Family Programmer’s Reference Manual for instruction set details) which includes support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the MCF52235 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities. The MAC implements a 4-stage arithmetic pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands and a complete set of instructions to process these data types. The EMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost. 1.2.3 Debug Module The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface users can access debug information, and on 112- and 121-lead packages real-time tracing capability is provided. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on Freescale’s 683xx family of parts. The MCF52235 supports Revision B+ of the ColdFire debug architecture (DEBUG_B+). The on-chip breakpoint resources include a total of nine programmable 32-bit registers: two address registers, two data registers (one data register and one data mask register), four 32-bit PC registers and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. The MCF52235’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging. To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52235 includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111). The full debug/trace interface is available only on the 112- and 121-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal. 1.2.4 JTAG The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a |
Số phần tương tự - MCF52231 |
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Mô tả tương tự - MCF52231 |
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