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AD708JNZ bảng dữ liệu(PDF) 10 Page - Analog Devices |
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10 / 16 page AD708 Rev. C | Page 10 of 16 THEORY OF OPERATION CROSSTALK PERFORMANCE The AD708 exhibits very low crosstalk as shown in Figure 25, Figure 26, and Figure 27. Figure 25 shows the offset voltage induced on Side B of the AD708 when Side A output is moving slowly (0.2 Hz) from −10 V to +10 V under no load. This is the least stressful situation to the part because the overall power in the chip does not change. Only the location of the power in the output device changes. Figure 26 shows the input offset voltage change to Side B when Side A is driving a 2 kΩ load. Here the power changes in the chip with the maximum power change occurring at 7.5 V. Figure 27 shows crosstalk under the most severe conditions. Side A is connected as a follower with 0 V input, and is forced to sink and source ±5 mA of output current. Power = (30 V)(5 mA) = 150 mW Even this large change in power causes only an 8 μV (linear) change in the input offset voltage of Side B. VOUTA = 2V/DIV 2V AVOUTA VIN = ±10V BVOUTB 10kΩ 10Ω 10Ω Figure 25. Crosstalk with No Load VOUTA = 2V/DIV 2V AVOUTA VIN = ±10V BVOUTB 10kΩ 2kΩ 10Ω 10Ω Figure 26. Crosstalk with 2 kΩ Load INA = 1mA/DIV 2V A VIN = ±10V IIN = ±5mA BVOUTB 10kΩ 2kΩ 10Ω 10Ω Figure 27. Crosstalk Under Forced Source and Sink Conditions |
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