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LM12454 bảng dữ liệu(PDF) 22 Page - National Semiconductor (TI) |
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LM12454 bảng dữ liệu(HTML) 22 Page - National Semiconductor (TI) |
22 / 36 page Pin Descriptions V A+VD+ Analog and digital supply voltage pins. The LM12(H)454/8’s supply voltage operating range is +3.0V to +5.5V. Accuracy is guaranteed only if V A+ and VD+ are connected to the same power supply. Each pin should have a parallel combina- tion of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors connected between it and ground. D0–D15 The internal data input/output TRI-STATE buffers are connected to these pins. These buffers are designed to drive capacitive loads of 100 pF or less. External buffers are necessary for driving higher load capacitances. These pins allows the user a means of instruction input and data output. With a logic high applied to the BW pin, data lines D8–D15 are placed in a high impedance state and data lines D0–D7 are used for instruction input and data output when the LM12(H)454/8 is con- nected to an 8-bit wide data bus. A logic low on the BW pin allows the LM12(H)454/8 to exchange information over a 16-bit wide data bus. RD Input for the active low READ bus control signal. The data input/output TRI-STATE buffers, as se- lected by the logic signal applied to the BW pin, are enabled when RD and CS are both low. This allows the LM12(H)454/8 to transmit information onto the data bus. WR Input for the active low WRITE bus control signal. The data input/output TRI-STATE buffers, as se- lected by the logic signal applied to the BW pin, are enabled when WR and CS are both low. This allows the LM12(H)454/8 to receive information from the data bus. CS Input for the active low Chip Select control signal. A logic low should be applied to this pin only during a READ or WRITE access to the LM12(H)454/8. The internal clocking is halted and conversion stops while Chip Select is low. Conver- sion resumes when the Chip Select input signal returns high. ALE Address Latch Enable input. It is used in systems containing a multiplexed data bus. When ALE is asserted high, the LM12(H)454/8 accepts infor- mation on the data bus as a valid address. A high-to-low transition will latch the address data on A0–A4 while the CS is low. Any changes on A0–A4 and CS while ALE is low will not affect the LM12(H)454/8. See Figure 10. When a non- multiplexed bus is used, ALE is continuously as- serted high. See Figure 11. CLK External clock input pin. The LM12(H)454/8 oper- ates with an input clock frequency in the range of 0.05 MHz to 10.0 MHz. A0–A4 The LM12(H)454/8’s address lines. They are used to access all internal registers, Conversion FIFO, and Instruction RAM. SYNC Synchronization input/output. When used as an output, it is designed to drive capacitive loads of 100 pF or less. External buffers are necessary for driving higher load capacitances. SYNC is an in- put if the Configuration register’s “I/O Select” bit is low. A rising edge on this pin causes the internal S/H to hold the input signal. The next rising clock edge either starts a conversion or makes a com- parison to a programmable limit depending on which function is requested by a programming instruction. This pin will be an output if “I/O Se- lect” is set high. The SYNC output goes high when a conversion or a comparison is started and low when completed. (See Section 2.2). An inter- nal reset after power is first applied to the LM12(H)454/8 automatically sets this pin as an input. BW Bus Width input pin. This input allows the LM12(H)454/8 to interface directly with either an 8- or 16-bit data bus. A logic high sets the width to 8 bits and places D8–D15 in a high impedance state. A logic low sets the width to 16 bits. INT Active low interrupt output. This output is designed to drive capacitive loads of 100 pF or less. Exter- nal buffers are necessary for driving higher load capacitances. An interrupt signal is generated any time a non-masked interrupt condition takes place. There are eight different conditions that can cause an interrupt. Any interrupt is reset by reading the Interrupt Status register. (See Section 2.3.) DMARQ Active high Direct Memory Access Request out- put. This output is designed to drive capacitive loads of 100 pF or less. External buffers are nec- essary for driving higher load capacitances. It goes high whenever the number of conversion results in the conversion FIFO equals a program- mable value stored in the Interrupt Enable regis- ter. It returns to a logic low when the FIFO is empty. GND LM12(H)454/8 ground connection. It should be connected to a low resistance and inductance analog ground return that connects directly to the system power supply ground. IN0–IN7 (IN0–IN3 LM12H454 LM12454) The eight (LM12(H)458) or four (LM12454) analog inputs. A given channel is selected through the instruction RAM. Any of the chan- nels can be configured as an independent single-ended input. Any pair of channels, whether adjacent or non-adjacent, can operate as a fully differential pair. S/H IN+ S/H IN− The LM12454’s non-inverting and inverting inputs to the internal S/H. MUXOUT+ MUXOUT− The LM12454’s non-inverting and inverting outputs from the internal multiplexer. V REF− The negative reference input. The LM12(H)454/8 operate with 0V ≤ V REF− ≤ V REF+. This pin should be bypassed to ground with a parallel combination of 10 µF and 0.1 µF (ceramic) capacitors. V REF+ The positive reference input. The LM12(H)454/8 operate with 0V ≤ V REF+ ≤ V A+. This pin should be bypassed to ground with a parallel combination of 10 µF and 0.1 µF (ceramic) capacitors. V REFOUT The internal 2.5V bandgap’s output pin. This pin should be bypassed to ground with a 100 µF capacitor. www.national.com 22 |
Số phần tương tự - LM12454_06 |
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Mô tả tương tự - LM12454_06 |
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