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ADM1192 bảng dữ liệu(PDF) 6 Page - Analog Devices

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ADM1192
Rev. B | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
1
SENSE
2
SETV
3
GND
4
TIMER 5
ALERT
10
CLRB
9
ADR
8
SDA
7
SCL
6
ADM1192
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCC
Positive Supply Input Pin. The operating supply voltage range is 3.15 V to 26 V. An undervoltage lockout (UVLO)
circuit resets the ADM1192 when a low supply voltage is detected.
2
SENSE
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across
a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this
voltage before it is digitized by the ADC.
3
SETV
Input Pin. The voltage driven onto this pin is compared with the output of the internal current sense amplifier.
The lower the voltage on the SETV, the lower the current level that causes the ALERT output to assert.
4
GND
Chip Ground Pin.
5
TIMER
Timer Input Pin. An external capacitor, CTIMER, sets the timing period for masking overcurrent conditions. This
timing period should be sufficient to allow the inrush current to completely charge up the load without
tripping an overcurrent fault. This makes the device robust against false triggering due to current transients.
6
SCL
I2C Clock Pin. Open-drain input; requires an external resistive pull-up.
7
SDA
I2C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up.
8
ADR
I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I2C
addresses.
9
CLRB
Clear Pin. A latched overcurrent condition can be cleared by pulling this pin low.
10
ALERT
Alert Output Pin. Active high, open-drain configuration. This pin asserts high when an overcurrent condition
is present. The level at which an overcurrent condition is detected depends on the voltage on the SETV pin.


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