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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADE8052Z-DWDL1 bảng dữ liệu(PDF) 9 Page - Analog Devices |
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ADE8052Z-DWDL1 bảng dữ liệu(HTML) 9 Page - Analog Devices |
9 / 144 page ![]() ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 9 of 144 Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY INPUTS VDD 3.13 3.3 3.46 V VBAT 2.4 3.3 3.7 V INTERNAL POWER SUPPLY SWITCH (VSWOUT) VBAT to VSWOUT On Resistance 22 Ω VBAT = 2.4 V VDD to VSWOUT On Resistance 10.2 Ω VDD = 3.13 V VBAT ←→ VDD Switching Open Time 40 ns BCTRL State Change and Switch Delay 18 μs VSWOUT Output Current Drive 1 6 mA POWER SUPPLY OUTPUTS VINTA 2.25 2.75 V VINTD 2.3 2.70 V VINTA Power Supply Rejection 60 dB VINTD Power Supply Rejection 50 dB POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 4 5.3 mA fCORE = 4.096 MHz, LCD and meter active 2.1 mA fCORE = 1.024 MHz, LCD and meter active 1.6 mA fCORE = 32.768 kHz, LCD and meter active 3.2 4.25 mA fCORE = 4.096 MHz, meter DSP active, metering ADC powered down 3 3.9 mA fCORE = 4.096 MHz, metering ADC and DSP powered down Current in PSM1 3.2 5.05 mA fCORE = 4.096 MHz, LCD active, VBAT = 3.7 V 880 μA fCORE = 1.024 MHz, LCD active Current in PSM2 38 μA LCD active with charge pump at 3.3 V + RTC 1.5 μA RTC only, TA = 25°C, VBAT = 3.3 V POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) 4 5.3 mA fCORE = 4.096 MHz, LCD and meter active 1 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 2 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 3 Test carried out with all the I/Os set to a low output level. 4 Delay between power supply valid and execution of first instruction by 8052 core. |
Số phần tương tự - ADE8052Z-DWDL1 |
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Mô tả tương tự - ADE8052Z-DWDL1 |
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