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LCZP bảng dữ liệu(PDF) 5 Page - Linear Technology

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Giải thích chi tiết về linh kiện  16-/14-/12-Bit VOUT DACs in 3mm3mm DFN
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nhà sản xuất  LINER [Linear Technology]
Trang chủ  http://www.linear.com
Logo LINER - Linear Technology

LCZP bảng dữ liệu(HTML) 5 Page - Linear Technology

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LTC2641/LTC2642
5
26412f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full
scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale.
LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale.
ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IIN
Digital Input Current
VIN = GND to VCC
±1
μA
CIN
Digital Input Capacitance
(Note 6)
310
pF
VH
Hysteresis Voltage
0.15
V
Power Supply
VDD
Supply Voltage
2.7
5.5
V
IDD
Supply Current, VDD
Digital Inputs = 0V or VDD
120
200
μA
PD
Power Dissipation
Digital Inputs = 0V or VDD, VDD = 5V
Digital Inputs = 0V or VDD, VDD = 3V
0.60
0.36
mW
mW
TIMING CHARACTERISTICS The denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t1
DIN Valid to SCLK Setup Time
10
ns
t2
DIN Valid to SCLK Hold Time
0ns
t3
SCLK Pulse Width High
9ns
t4
SCLK Pulse Width Low
9ns
t5
⎯C⎯S Pulse High Width
10
ns
t6
LSB SCLK High to ⎯C⎯S High
8ns
t7
⎯C⎯S Low to SCLK High
8ns
t8
⎯C⎯S High to SCLK Positive Edge
8ns
t9
⎯C⎯L⎯R Pulse Width Low
15
ns
fSCLK
SCLK Frequency
50% Duty Cycle
50
MHz
VDD High to ⎯C⎯S Low (Power-Up Delay)
30
μs
Note 4: ROUT tolerance is typically ±20%.
Note 5: Reference input resistance is code dependent. Minimum is at
871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar
mode.
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
tested.


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