công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
GS1582-IBE3 bảng dữ liệu(PDF) 5 Page - Gennum Corporation |
|
GS1582-IBE3 bảng dữ liệu(HTML) 5 Page - Gennum Corporation |
5 / 114 page GS1582 Data Sheet 40117 - 1 November 2007 5 of 114 List of Figures Figure 2-1: Maximum Pb-free Solder Reflow Profile ..................................................21 Figure 3-1: Differential Output Stage (SDO/SDO) .....................................................22 Figure 3-2: Charge Pump Current Setting Resistor (CP_RES) ..................................22 Figure 3-3: PLL Loop Filter ........................................................................................23 Figure 3-4: VCO Input ................................................................................................23 Figure 3-5: Digital Input Pin with Weak Pull Up(>33kW) (ACLK[2:1], WCLK[2:1], AIN[4:1], PCLK, DIN[19:0]) .................................................24 Figure 3-6: 5V Tolerant Input Pin (All Other Input Pins) .............................................24 Figure 3-7: Digital Output Pin with High Impedance Mode (LOCKED, AUDIO_INT, SDOUT_TDO) .....................................................................24 Figure 4-1: PCLK to Data Timing ...............................................................................26 Figure 4-2: H_Blanking, V_Blanking, F_Digital Timing ..............................................29 Figure 4-3: HSYNC:VSYNC:DE Input Timing 1280 x 720p @ 59.94/60 ....................31 Figure 4-4: HSYNC:VSYNC:DE Input Timing 1920 x 1080i @ 59.94/60 ...................31 Figure 4-5: HSYNC:VSYNC:DE Input Timing 720 (1440) x 480i @ 59.94/60 ...........32 Figure 4-6: HSYNC:VSYNC:DE Input Timing 1280 x 720p @ 50 ..............................33 Figure 4-7: HSYNC:VSYNC:DE Input Timing 1920 x 1080i @ 50 .............................33 Figure 4-8: HSYNC:VSYNC:DE Input Timing 720 (1440) x 576 @ 50 ......................34 Figure 4-9: DVB-ASI FIFO Implementation using the GS1582 ..................................35 Figure 4-10: Audio Multiplexer Top Level ..................................................................37 Figure 4-11: Ancillary Data Packet Placement Example ............................................39 Figure 4-12: SD Audio Data Packet Structure ...........................................................42 Figure 4-13: SD Extended Audio Data Packet Structure ...........................................43 Figure 4-14: HD Audio Data Packet Structure ...........................................................43 Figure 4-15: SD Audio Control Packet Structure .......................................................45 Figure 4-16: HD Audio Control Packet Structure .......................................................46 Figure 4-17: Audio Group Replacement Example (HD Formats) ...............................49 Figure 4-18: ACLK to Data & Control Signal Input Timing .........................................51 Figure 4-19: AES/EBU Sub-frame Formatting ...........................................................54 Figure 4-20: AES/EBU Audio Input Format ................................................................54 Figure 4-21: Serial Audio Input: Left Justified; MSB First ..........................................54 Figure 4-22: Serial Audio Input: Left Justified; LSB First ...........................................55 Figure 4-23: Serial Audio Input: Right Justified; MSB First ........................................55 Figure 4-24: Serial Audio Input: Right Justified; LSB First .........................................55 Figure 4-25: I2S Audio Input .......................................................................................55 Figure 4-26: Gennum Serial Peripheral Interface (GSPI) ..........................................77 Figure 4-27: Command Word .....................................................................................78 Figure 4-28: Data Word ..............................................................................................78 Figure 4-29: GSPI Read Mode Timing .......................................................................79 Figure 4-30: GSPI Write Mode Timing .......................................................................79 Figure 4-31: In-Circuit JTAG ....................................................................................106 Figure 4-32: System JTAG .......................................................................................106 Figure 4-33: Reset Pulse .........................................................................................107 |
Số phần tương tự - GS1582-IBE3 |
|
Mô tả tương tự - GS1582-IBE3 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |