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MC88LV915T bảng dữ liệu(PDF) 9 Page - Motorola, Inc

tên linh kiện MC88LV915T
Giải thích chi tiết về linh kiện  Low Voltage Low Skew CMOS PLL Clock Driver, 3-State
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
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MC88LV915T bảng dữ liệu(HTML) 9 Page - Motorola, Inc

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MOTOROLA
MC88LV915T System Level Testing Functionality
3–state functionality has been added to the 100MHz version of the MC88LV915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The
2X_Q output will be the inverse of the SYNC signal in this mode. If the 3–state functionality will be used, a pull–up or pull–
down resistor must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high
impedance.
With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can
also be used for low frequency board testing.
Note: If the outputs are put into 3–state during normal PLL operation, the loop will be broken and phase–lock will be lost. It
will take a maximum of 10mS (tLOCK spec) to regain phase–lock after the OE/RST pin goes back high.
Figure 4. Representation of a Potential Multi–Processing Application Utilizing the MC88LV915T
for Frequency Multiplication and Low Board–to–Board Skew
MC88LV915T
PLL
2f
2f
MC88LV915T
PLL
SYSTEM
CLOCK
SOURCE
CPU
CARD
CPU
CARD
MEMORY
CARDS
CMMU
CMMU
CMMU
CMMU
CMMU
CPU
CLOCK
@ f
CMMU
CMMU
CMMU
CMMU
CMMU
CPU
2f
PLL
MEMORY
CONTROL
CLOCK @ 2f
AT POINT OF USE
CLOCK @ 2f
AT POINT OF USE
DISTRIBUTE
CLOCK @ f
MC88LV915T


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