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10 / 173 page List of figures ST10F271 10/173 Figure 49. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. . . . 153 Figure 51. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 154 Figure 52. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 155 Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 156 Figure 54. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 159 Figure 55. Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE . . . . . . 160 Figure 56. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 161 Figure 57. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 162 Figure 58. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 59. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 60. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 61. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 62. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 63. 144-pin low profile quad flat package (10x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure 64. PQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 |
Số phần tương tự - ST10F271Z1T3 |
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