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10 / 175 page ST10F272M 10/176 Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 156 Figure 54. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 159 Figure 55. External memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE . . . . . 160 Figure 56. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 161 Figure 57. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 162 Figure 58. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 59. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 60. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 61. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 62. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 63. PQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 64. LQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 |
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