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TC74HC109AP/AF/AFN
2007-10-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC109AP,TC74HC109AF,TC74HC109AFN
Dual J-K Flip-Flop with Preset and Clear
The TC74HC109A is a high speed CMOS J-
K FLIP FLOP
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
In accordance with the logic levels applied to the J and K
inputs, the outputs change state on the positive going transition
of the clock pulse.
CLR
and PR are independent of the clock and are
accomplished by a low logic level on the corresponding input.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: fmax = 63 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2~6 V
• Pin and function compatible with 74LS109
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC109AP
TC74HC109AF
TC74HC109AFN
Weight
DIP16-P-300-2.54A
: 1.00 g (typ.)
SOP16-P-300-1.27A
: 0.18 g (typ.)
SOL16-P-150-1.27
: 0.13 g (typ.)


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