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ADS8519IDBR bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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ADS8519IDBR bảng dữ liệu(HTML) 6 Page - Texas Instruments |
6 / 25 page www.ti.com ADS8519 SLAS462 – JUNE 2007 Terminal Functions TERMINAL DESCRIPTION NAME SSOP QFN NO. I/O NO. AGND1 2 30 – Analog ground. Used internally as ground reference point. Minimal current flow. AGND2 9 6 – Analog ground BUSY 25 25 O Busy output. Falls when a conversion is started, and remains low until the conversion is completed and the data is latched into the output shift register. CS 24 22 – Chip select. Internally ORed with R/C. CAP 6 3 DATA 17 15 O Serial data output. Data is synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock mode, after 16 bits of data, the ADS8519 outputs the level input on TAG as long as CS is low and R/C is high (see Figure 8 and Figure 9). If EXT/INT is low, data is valid on both the rising and falling edges of DATACLK, and between conversions DATA stays at the level of the TAG input when the conversion was started. DATACLK 16 14 I/O Either an input or an output depending on the EXT/INT level. Output data is synchronized to this clock. If EXT/INT is low, DATACLK transmits 16 pulses after each conversion, and then remains low between conversions. DGND 14 12 – Digital ground EXT/INT 13 11 – Selects external or internal clock for transmitting data. If high, data is output synchronized to the clock input on DATACLK. If low, a convert command initiates the transmission of the data from the previous conversion, along with 16-clock pulses output on DATACLK. NC 5, 8, 10, 1, 2, 5, 7, – No connect 11, 18, 8, 9, 16, 20, 22, 17, 19, 23 21, 23, 24 PWRD 26 26 I Power down input. If high, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversion are maintained in the output shift register. R/C 21 20 I Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low, or a falling edge on CS with R/C high, transmits a pulse on SYNC and initiates the transmission of data from the previous conversion. REF 7 4 I/O Reference input/output. Outputs internal 4.096-V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.2- μF tantalum capacitor. R1IN 1 29 I Analog input. See Table 3 for input range connections. R2IN 3 31 I Analog input. See Table 3 for input range connections. R3IN 4 32 I Analog input. See Table 3 for input range connections. SB/BTC 12 10 O Select straight binary or binary 2's complement data output format. If high, data is output in a straight binary format. If low, data is output in a binary 2's complement format. SYNC 15 13 O Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high and at least one external clock pulse has occured when not in the read mode. See the external clock modes desciptions. TAG 19 18 I Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output on DATA with a delay that is dependent on the external clock mode. See Figure 8 and Figure 9. VANA 27 28 I Analog supply input. Nominally +5 V. Connect directly to pin 20, and decouple to ground with 0.1- μF ceramic and 10-μF tantalum capacitors. VDIG 28 27 I Digital supply input. Connect directly to pin 19. Must be ≤ VANA. 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated ADS8519 |
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