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74LV86 bảng dữ liệu(PDF) 3 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  Quad 2-input exclusive-OR gate
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74LV86_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 27 November 2007
3 of 15
NXP Semiconductors
74LV86
Quad 2-input exclusive-OR gate
5.2 Pin description
6.
Functional description
7.
Limiting values
Table 2.
Pin description
Symbol
Pin
Description
1A
1
data input
1B
2
data input
1Y
3
data output
2A
4
data input
2B
5
data input
2Y
6
data output
GND
7
ground (0 V)
3Y
8
data output
3A
9
data input
3B
10
data input
4Y
11
data output
4A
12
data input
4B
13
data input
VCC
14
supply voltage
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
Output
nA
nB
nY
LLL
LH
H
HL
H
HHL
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
−0.5
+7.0
V
IIK
input clamping current
VI < −0.5 V or VI >VCC + 0.5 V
[1] -
±20
mA
IOK
output clamping current
VO < −0.5 V or VO >VCC + 0.5 V
[1] -
±50
mA
IO
output current
VO = −0.5 V to (VCC + 0.5 V)
-
±25
mA
ICC
supply current
-
50
mA
IGND
ground current
−50
-
mA
Tstg
storage temperature
−65
+150
°C


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