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ADM13305-25ARZ1 bảng dữ liệu(PDF) 10 Page - Analog Devices |
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ADM13305-25ARZ1 bảng dữ liệu(HTML) 10 Page - Analog Devices |
10 / 12 page ADM13305 Rev. 0 | Page 10 of 12 THEORY OF OPERATION The ADM13305 is a dual voltage supervisor designed to monitor two supplies and provide a reset signal to DSP and microprocessor-based systems. There are five models available, all of which feature a combina- tion of internally pretrimmed undervoltage threshold options for monitoring 1.8 V, 2.5 V, 3.3 V, and 5 V supplies. There is also an adjustable input option with an undervoltage threshold of 0.6 V. The ADM13305-18, ADM13305-25, and ADM13305-33 have two internally fixed thresholds, while the ADM13305-4 and ADM13305-5 offer one internally fixed threshold and one externally programmable threshold via a resistor string. See the Ordering Guide for a list of all available options. INPUT CONFIGURATION The ADM13305 is powered through VDD. To increase noise immunity in noisy applications, place a 0.1 μF capacitor between the VDD input and ground. The SENSEv inputs are resistant to short power supply glitches. Do not allow an unused SENSEv input to float or to be grounded, instead connect it to a supply voltage greater than its specified threshold voltage. Typically, the threshold voltage at each adjustable SENSEv input is 0.6 V. To monitor a voltage greater than 0.6 V, connect a resistor divider network to the device as depicted in Figure 13, where, ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + = R2 R2 R1 V MONITERED V 6 . 0 R1 R2 MONITORED VOLTAGE VREF = 0.6V Figure 13. Setting the Adjustable Monitor RESET OUTPUT The reset outputs are guaranteed to be in the correct state for VDD down to 1.1 V. During power-up, RESET is asserted when the supply voltage becomes greater than 1.1 V. SENSEv V(NOM) 0 1 VIT– RESET td td t t Figure 14. Reset Timing Diagram Once the supplies monitored at the SENSEv pins rise above their associated threshold level, the RESET signal remains low for the reset timeout period before deasserting. Subsequently, if either of the supplies monitored by the SENSEv pins falls below its associated threshold the RESET output reasserts. The ADM13305 features both an active-low, push-pull RESET output and an active-high, push-pull RESET output. WATCHDOG TIMER The ADM13305 features a watchdog timer that monitors microprocessor activity. A timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI). If the timer counts through the preset watchdog timeout period of 1.6 sec, RESET is asserted, as shown in . Figure 15 The microprocessor is required to toggle the WDI pin to avoid being reset. Therefore, failure of the microprocessor to toggle WDI within the timeout period indicates a code execution error and the reset pulse generated restarts the microprocessor in a known state. The watchdog timer can be disabled by leaving WDI floating. 0 1 RESET 0 1 WDI tWD td t t Figure 15. Watchdog Timing Diagram |
Số phần tương tự - ADM13305-25ARZ1 |
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Mô tả tương tự - ADM13305-25ARZ1 |
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