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STK14EC8-TF15TR bảng dữ liệu(PDF) 5 Page - Simtek Corporation |
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STK14EC8-TF15TR bảng dữ liệu(HTML) 5 Page - Simtek Corporation |
5 / 18 page STK14EC8 5 Simtek Confidential April, 2007 Document Control #ML0060 Rev 1.0 Preliminary SRAM READ CYCLES #1 & #2 Note c: W must be high during SRAM READ cycles. Note d: Device is continuously selected with E and G both low Note e: Measured ± 200mV from steady state output voltage. Note f: HSB must remain high during READ and WRITE cycles. SRAM READ CYCLE #1: Address Controlledc,d,f SRAM READ CYCLE #2: E Controlledc,f NO. SYMBOLS PARAMETER STK14EC8-15 STK14EC8-25 STK14EC8-45 UNITS #1 #2 Alt. MIN MAX MIN MAX MIN MAX 1tELQV tACS Chip Enable Access Time 15 25 45 ns 2tAVAV c tAVAV c tRC Read Cycle Time 15 25 45 ns 3tAVQV d tAVQV d tAA Address Access Time 15 25 45 ns 4tGLQV tOE Output Enable to Data Valid 10 12 20 ns 5tAXQX d tAXQX d tOH Output Hold after Address Change 3 3 3 ns 6tELQX tLZ Chip Enable to Output Active 3 3 3 ns 7tEHQZ e tHZ Chip Disable to Output Inactive 7 10 15 ns 8tGLQX tOLZ Output Enable to Output Active 0 0 0 ns 9tGHQZ e tOHZ Output Disable to Output Inactive 7 10 15 ns 10 tELICCH b tPA Chip Enable to Power Active 0 0 0 ns 11 tEHICCL b tPS Chip Disable to Power Standby 15 25 45 ns DATA VALID 5 tAXQX 3 tAVQV DQ (DATA OUT) ADDRESS 2 tAVAV 6 tELQX STANDBY DATA VALID 4 tGLQV DQ (DATA OUT) E ADDRESS 2 tAVAV G ICC ACTIVE 10 tELICCH 11 tEHICCL 7 tEHQZ 8 tGLQX 1 tELQV 9 tGHQZ |
Số phần tương tự - STK14EC8-TF15TR |
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Mô tả tương tự - STK14EC8-TF15TR |
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