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LANSDALE Semiconductor, Inc.
ML145050, ML145051
BLOCK DIAGRAM
SUCCESSIVE APPROXIMATION
REGISTER
1
2
3
4
5
6
7
8
9
11
12
17
16
19
15
18
19
10-BIT RC DAC
WITH SAMPLE AND HOLD
DATA REGISTER
14
13
VAG
Vref
AUTO-ZEROED
COMPARATOR
MUX ADDRESS
REGISTER
DIGITAL CONTROL
LOGIC
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
CS
Din
Dout
SCLK
EOC (ML145051 ONLY)
ADCLK (ML145050 ONLY)
MUX OUT
PIN 20 = VDD
PIN 10 = VSS
ANALOG
MUX
INTERNAL
TEST
VOLTAGES
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage (Referenced to VSS)
– 0.5 to + 6.0
V
Vref
DC Reference Voltage
VAG to VDD + 0.1
V
VAG
Analog Ground
VSS – 0.1 to Vref
V
Vin
DC Input Voltage, Any Analog or Digital
Input
VSS – 0.5 to
VDD + 0.5
V
Vout
DC Output Voltage
VSS – 0.5 to
VDD + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
IDD, ISS DC Supply Current, VDD and VSS Pins
± 50
mA
Tstg
Storage Temperature
– 65 to 150
C
TL
Lead Temperature, 1 mm from Case for
10 Seconds
260
C
* Maximum Ratings are those values beyond which damage to the device may occur. Func-
tional operation should be restricted to the Operation Ranges below..
OPERATION RANGES (Applicable to Guaranteed Limits)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage, Referenced to VSS
4.5 to 5.5
V
Vref
DC Reference Voltage
VAG + 4.0 to VDD + 0.1
V
VAG
Analog Ground
VSS – 0.1 to Vref – 4.0
V
VAI
Analog Input Voltage (See Note)
VAG to Vref
V
Vin, Vout Digital Input Voltage, Output Voltage
VSS to VDD
V
TA
Ambient Operating Temperature
– 40 to 125
C
NOTE: Analog input voltages greater than Vref convert to full scale. Input voltages less than VAG convert to zero. See Vref and VAG pin
descriptions.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications
of any voltage higher than maximum rated
voltages to this high-impedance circuit. For
proper operation, Vin and Vout should be
constrained to the range VSS ≤(Vin or Vout) ≤
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VDD). Unused outputs must be left
open.
Issue B


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