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MC145026D bảng dữ liệu(PDF) 8 Page - LANSDALE Semiconductor Inc. |
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MC145026D bảng dữ liệu(HTML) 8 Page - LANSDALE Semiconductor Inc. |
8 / 19 page www.lansdale.com Page 8 of 19 Issue 0 LANSDALE Semiconductor, Inc. ML145026, ML145027, ML145028 acknowledged; a trinary open at the ML145026 encoder is decoded as a high level (logic 1). Din Data In (Pin 9) This pin is the serial data input to the decoder. The input voltage must be at CMOS logic levels. The signal source driv- ing this pin must be DC coupled. R1,C1 Resistor 1, Capacitor 1 (Pins 6, 7) As shown in Figures 2 and 3, these pins accept a resistor and capacitor that are used to determine whether a narrow pulse or wide pulse has been received. The time constant R1 x C1 should be set to 1.72 encoder clock periods: R1 C1 = 3.95 RTC CTC R2/C2 Resistor 2/Capacitor 2 (Pin 10) As shown in Figures 2 and 3, this pin accepts a resistor and capacitor that are used to detect both the end of a received word and the end of a transmission. The time constant R2 x C2 should be 33.5 encoder clock periods (four data periods per Figure 11): R2 C2 = 77 RTC CTC. This time constant is used to determine whether the Din pin has remained low for four data periods (end of transmission). A separate on–chip com- parator looks at the voltage–equivalent two data periods (0.4 R2 C2) to detect the dead time between received words within a transmission. VT Valid Transmission Output (Pin 11) This valid transmission output goes high after the second word of an encoding sequence when the following conditions are satisfied: 1. the received addresses of both words match the local de-coder address, and 2. the received data bits of both words match. VT remains high until either a mismatch is received or no input signal is received for four data periods. VSS Negative Power Supply (Pin 8) The most–negative supply potential. This pin is usually ground. VDD Positive Power Supply (Pin 16) The most–positive power supply pin. |
Số phần tương tự - MC145026D |
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Mô tả tương tự - MC145026D |
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