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ADS5232IPAG bảng dữ liệu(PDF) 7 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  Dual, 12-Bit, 65MSPS, 3.3V Analog-to-Digital Converter
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ADS5232IPAG bảng dữ liệu(HTML) 7 Page - Texas Instruments

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Analog
Input
CLK
DATA[D11:D0]
DV
OE
DATA
D11:D0
t
OE
t
OE
t
DV
t
1
t
2
t
C
t
A
N + 1
N + 2
N + 4
N + 3
N
TIMING CHARACTERISTICS
(1)
ADS5232
SBAS294A – JUNE 2004 – REVISED MARCH 2006
TIMING DIAGRAM
Typical values at T
A = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty
cycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
65MSPS With PLL ON
tA Aperture Delay
2.1
ns
Aperture Jitter
1.0
ps
t1 Data Setup Time(2)
2
3.2
ns
t2 Data Hold Time(3)
6.3
8.5
ns
tD Data Latency
6
Clocks
tDR, tDF Data Rise/Fall Time(4)
0.5
2
3
ns
Data Valid (DV) Duty Cycle
30
40
55
%
tDV Input Clock Rising to DV Fall Edge
10
11.5
14
ns
(1)
Specifications assured by design and characterization; not production tested.
(2)
Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV.
(3)
Measured from the 50% point of the falling edge of DV to the data becoming invalid.
(4)
Measured between 20% to 80% of logic levels.
7
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