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FM20L08 bảng dữ liệu(PDF) 5 Page - Ramtron International Corporation |
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FM20L08 bảng dữ liệu(HTML) 5 Page - Ramtron International Corporation |
5 / 14 page FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 5 of 14 Supply Voltage Monitor An internal voltage monitor circuit continuously checks the VDD supply voltage. When VDD is below the specified threshold VTP, the monitor asserts the /LVL signal to an active-low state. The FM20L08 locks out access to the memory when VDD is below the trip voltage. This prevents the system from accessing memory when VDD is too low and inadvertently corrupting the data. The /LVL signal should not be used as a system reset signal because the system host may attempt to write data to the FM20L08 below its specified operating voltage. The /LVL pin may be used as a status indicator that the memory is locked out. On power up, the /LVL signal will begin in a low state signifying that VDD is below the VTP threshold. It will remain low as long as VDD is below that level. Once VDD rises above VTP, a hold-off timer will begin creating the delay tPULV. Once this delay has elapsed, the /LVL signal will go high or inactive. At this time the memory can be accessed. The memory is ready for access prior to tPU as shown in the Electrical Specifications section. The /LVL signal will remain high until VDD drops below the threshold. Software Write Protection (Applies only to “-TG1” device. The –TG device does not have this Write Protect feature. See Ordering Information on page 1) The 128Kx8 address space is divided into 8 sectors (blocks) of 16Kx8 each. Each sector can be individually software write-protected and the settings are nonvolatile. A unique address and command sequence invokes the write protection mode. To modify write protection, the system host must issue six read commands and two write commands. The specific sequence of read addresses must be provided in order to access to the write protect mode. Following the read address sequence, the host must write a data byte that specifies the desired protection state of each sector. For confirmation, the system must then write the complement of the protection byte immediately following the protection byte. Any error that occurs including read addresses in the wrong order, issuing a seventh read address, or failing to complement the protection value will leave the write protection unchanged. The write-protect state machine monitors all addresses, taking no action until the write-protect read/write sequence occurs. During the address sequence, each read will occur as a valid operation and data from the corresponding addresses will be driven onto the data bus. Any address that occurs out of sequence will cause the software protection state machine to start over. After the address sequence is completed, the next operation must be a write cycle. The data byte contains the write-protect settings. This value will not be written to the memory array, so the write address is ignored. Rather the byte will be held pending the next cycle, which must be a write of the data complement to the protection settings. If the complement is correct, the write protect settings will be updated. If not, the process is aborted and the address sequence starts over. The data value written after the correct six addresses will not be entered into memory. The protection data byte consists of 8-bits, each associated with the write protect state of a sector. Setting a bit to 1 write protects the corresponding sector; a 0 enables writes for that sector. The following table shows the write-protect sectors with the corresponding bit that controls the write-protect setting. Write Protect Sectors – 16K x8 blocks Sector 7 1FFFFh – 1C000h Sector 6 1BFFFh – 18000h Sector 5 17FFFh – 14000h Sector 4 13FFFh – 10000h Sector 3 0FFFFh – 0C000h Sector 2 0BFFFh – 08000h Sector 1 07FFFh – 04000h Sector 0 03FFFh – 00000h The write-protect address sequence follows: 1. 05555h * 2. 1AAAAh 3. 03333h 4. 1CCCCh 5. 100FFh 6. 0FF00h 7. 1AAAAh 8. 1CCCCh 9. 0FF00h 10. 00000h * If /CE is low entering the sequence, then an address of 00000h must precede 05555h. The address sequence provides a very secure way of modifying the protection. The correct address sequence has a 1 in 5 x 10 30 chance of occurring accidentally. A flow chart of the entire write protect operation is shown in Figure 2. As mentioned above, write-protect settings are nonvolatile. The factory default is unprotected. |
Số phần tương tự - FM20L08_07 |
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Mô tả tương tự - FM20L08_07 |
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