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ADS8506

SLAS484A – SEPTEMBER 2007 – REVISED OCTOBER 2007

Terminal Functions

TERMINAL

DIGITAL

DESCRIPTION

I/O

NO.

NAME

1

Analog Input.

2

AGND1

Analog sense ground. Used internally as ground reference point. Minimal current flow

3

Analog Input.

4

CAP

Reference buffer output. 2.2-

μF Tantalum capacitor to ground.

5

REF

Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system

reference. In both cases, bypass to ground with a 2.2-

μF tantalum capacitor.

6

AGND2

Analog ground

7

SB/BTC

I

Selects straight binary or binary 2's complement for output data format. if high, data is output in a

straight binary format. If low, data is output in a binary 2's complement format.

8

EXT/INT

I

Selects external/Internal data clock for transmitting data. If high, data is output synchronized to

the clock input on DATACLK. If low, a convert command initiates the transmission of the data

from the previous conversion, along with 12-clock pulses output on DATACLK.

9

D7

O

Data bit 3 if BYTE is high. Data bit 11 (MSB) if BYTE is low. Hi-Z when CS is high and/or R/C is

low. Leave unconnected when using serial output.

10

D6

O

Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. Hi-Z when CS is high and/or R/C is low.

11

D5

O

Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. Hi-Z when CS is high and/or R/C is low.

12

D4

O

Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. Hi-Z when CS is high and/or R/C is

low.

13

D3

O

Ground if BYTE is high. Data bit 7 if BYTE is low. Hi-Z when CS is high and/or R/C is low.

14

DGND

Digital ground

15

D2

O

Ground if BYTE is high. Data bit 6 if BYTE is low. Hi-Z when CS is high and/or R/C is low.

16

D1

O

Ground if BYTE is high. Data bit 5 if BYTE is low. Hi-Z when CS is high and/or R/C is low.

17

D0

O

Ground if BYTE is high. Data bit 4 if BYTE is low. Hi-Z when CS is high and/or R/C is low.

18

DATACLK

I/O

Either an input or an output depending on the EXT/INT level. Output data is synchronized to this

clock. If EXT/INT is low, DATACLK transmits 12 pulses after each conversion, and then remains

low between conversions.

19

SDATA

O

Serial data output. Data is synchronized to DATACLK, with the format determined by the level of

SB/BTC. In the external clock mode, after 12 bits of data, the ADC outputs the level input on

TAG as long as CS is low and R/C is high. If EXT/INT is low, data is valid on both the rising and

falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG input

when the conversion was started.

20

TAG

I

Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output

on DATA with a delay that is dependent on the external clock mode.

21

BYTE

I

Selects 8 most significant bits (low) or 8 least significant bits (high) on parallel output pins.

22

R/C

I

Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the

hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of

the data results from the previous conversion.

23

CS

I

Internally ORed with R/C. If R/C is low, a falling edge on CS initiates a new conversion. If

EXT/INT is low, this same falling edge will start the transmission of serial data results from the

previous conversion.

24

BUSY

O

At the start of a conversion, BUSY goes low and stays low until the conversion is completed and

the digital outputs have been updated.

25

PWRD

I

Power down input. If high, conversions are inhibited and power consumption is significantly

reduced. Results from the previous conversion are maintained in the output shift register.

26

REFD

I

REFD High shuts down the internal reference. External reference will be required for

conversions.

27

Analog Supply. Nominally +5 V. Decouple with 0.1-

μF ceramic and 10-μF tantalum capacitors.

28

Digital Supply. Nominally +5 V. Connect directly to pin 27. Must be

Copyright © 2007, Texas Instruments Incorporated

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