Undervoltage Lockout

Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully

functional before the output stage is enabled. The positive power supply terminal (Vcc) and the

reference output (Vref) are each monitored by separate comparators. Each has built-in hysteresis

to prevent erratic output behavior as their respective thresholds are crossed. The large hysteresis

and low start-up current of the TS3842B makes it ideally suited in off-line converter applications

where efficient bootstrap start-up technique (Figure 33). 36V zener is connected as a shunt

regulator from Vcc to ground. Its purpose is to protect the IC from excessive voltage that can

occur during system start-up. The minimum operating voltage for the TS3842B is 11V.

Output

These devices contain a single totem pole output stage that was specifically designed for direct

drive of power MOSFET’s. It is capable of up to ±1.0A peak drive current and has a typical rise and

fall time of 50 ns with a 1.0nF load. Additional internal circuitry has been added to keep the output

in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the

need for an external pull-down resistor.

The SOP-8 surface mount package provides separate pins for Vc(output supply) and Power Ground.

Proper implementation will significantly reduce the level of switching transient noise imposed on

the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level.

The separate Vc supply input allows the designer added flexibility in tailling the drive voltage

independent of Vcc. A zener clamp is typically connected to this input when driving power MOSFETs

in systems where Vcc is greater than 20V. Figure 25 shows proper power and control ground

connections in a current sensing power MOSFET application.

Reference

The 5.0V bandgap reference is trimmed to ±2.0% on the TS3842B. Its primary purpose to supply

charging current to the oscillator timing capacitor. The reference has short circuit protection and

is capable of providing in excess of 20mA for powering additional control system circuitry.

Design Considerations

Do not attempt to construct the converter on wire wrap or plug-in prototype boards.

High frequency circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually

caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs.

Noise immunity can be improved by lowering circuit impedances at these points. The printed

circuit layout should contain a ground plane with low-current signal and high-current switch and

output grounds returning separate paths back to the input filter capacitor. Ceramic bypass capacitors

(0.1

µF) connected directly to Vcc,Vc, and Vref may be required depending upon circuit layout.