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STAC9750 bảng dữ liệu(PDF) 4 Page - Integrated Device Technology

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Giải thích chi tiết về linh kiện  VALUE-LINE TWO-CHANNEL AC??7 CODECS
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STAC9750 bảng dữ liệu(HTML) 4 Page - Integrated Device Technology

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STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
IDT™
4
STAC9750/9751
V 5.8 103106
VALUE-LINE TWO-CHANNEL AC’97 CODECS
LIST OF TABLES
Table 1. STAC9751 Analog Performance Characteristics ............................................................................. 13
Table 2. Cold Reset Specifications ................................................................................................................ 15
Table 3. Warm Reset Specifications .............................................................................................................. 15
Table 4. Clocks Specifications ....................................................................................................................... 16
Table 5. Clock Mode Configuration ............................................................................................................... 16
Table 6. Data Setup and Hold Specifications ................................................................................................ 17
Table 7. Signal Rise and Fall Times Specifications ....................................................................................... 17
Table 8. AC-Link Low Power Mode Timing Specifications ............................................................................ 18
Table 9. ATE Test Mode Specifications ......................................................................................................... 18
Table 10. STAC9750/9751 Available Data Streams ...................................................................................... 21
Table 11. Command Address Port Bit Assignments ...................................................................................... 23
Table 12. Command Data Port Bit Assignments ........................................................................................... 24
Table 13. Status Address Port Bit Assignments ............................................................................................ 27
Table 14. Status Data Port Bit Assignments .................................................................................................. 27
Table 15. Programming Registers ................................................................................................................. 34
Table 16. Play Master Volume Register ........................................................................................................ 35
Table 17. PC_BEEP Register ........................................................................................................................ 36
Table 18. Analog Mixer Input Gain Register .................................................................................................. 37
Table 19. Record Select Control Registers ................................................................................................... 39
Table 20. Record Gain Registers ................................................................................................................. 39
Table 21. General Purpose Register ............................................................................................................. 40
Table 22. 3D Control Registers .................................................................................................................... 40
Table 23. Powerdown Status Registers ......................................................................................................... 42
Table 24. Extended Audio ID ......................................................................................................................... 43
Table 25. Slot assignment relationship between SPSA1 and SPSA0 ........................................................... 45
Table 26. STAC9750/9751 AMAP compliant ................................................................................................. 45
Table 27. Hardware Supported Sample Rates .............................................................................................. 45
Table 28. SPDIF Control ............................................................................................................................... 46
Table 29. Extended Moden Status and Control ............................................................................................. 47
Table 31. GPIO Pin Polarity/Type Register ................................................................................................... 48
Table 32. GPIO Pin Sticky Register ............................................................................................................... 48
Table 30. GPIO Pin Configuration Register ................................................................................................... 48
Table 33. GPIO Pin Mask Register ................................................................................................................ 49
Table 35. Digital Audio Control Register ........................................................................................................ 50
Table 34. GPIO Pin Status Register .............................................................................................................. 50
Table 36. ADC data on AC LINK ................................................................................................................... 52
Table 37. Mic Boost Select ............................................................................................................................ 52
Table 38. Analog Current Adjust ................................................................................................................... 53
Table 39. GPIO Access Registers (74h) ........................................................................................................ 54
Table 40. Low Power Modes ......................................................................................................................... 56
Table 41. CODEC ID Selection ..................................................................................................................... 58
Table 42. Secondary CODEC Register Access Slot 0 Bit Definitions ........................................................... 59
Table 43. Digital Connection Signals ............................................................................................................. 62
Table 44. Analog Connection Signals ........................................................................................................... 63
Table 45. Filtering and Voltage References .................................................................................................. 64
Table 46. Power and Ground Signals ............................................................................................................ 64


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